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PDF ( 数据手册 , 数据表 ) QDCF-8GUH1I

零件编号 QDCF-8GUH1I
描述 (QDCF-xxx(M/G)UH1(I)) Compact Flash
制造商 Quantum Digital
LOGO Quantum Digital LOGO 


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QDCF-8GUH1I 数据手册, 描述, 功能
Quantum Digital Compact Flash 
 
General Description and Key Features 
 
Quantum Digital’s flash storage products meet the latest industry 
compliance and regulatory standards including UL, FCC, and 
RoHS. Each device incorporates a proprietary cutting edge flash 
memory controller (hyperstone f3 series) that provides the 
greatest flexibility to customerspecific applications while 
supporting key flash management features resulting in the 
industry’s highest reliability and endurance. Key features include: 
Builtin ECC engine detects up to 5byte and corrects up to 4byte 
errors Sophisticated block management and wear leveling 
algorithms guarantees 2,000,000 write/erase cycles Powerdown 
data protection ensures data integrity and errors in case of power 
loss Lifecycle management feature allows users to monitor the 
device’s block management Quantum Digital’s CF Card is the 
product of choice in applications requiring high reliability 
and high tolerance to shock, vibration, humidity, altitude, ESD, 
and temperature. The rugged industrial design combined with 
industrial temperature (40°C to 85°C) testing and adherence to 
rigid JEDEC JESD22 standards ensures flawless execution in the 
harshest environments.     
 
In addition to custom hardware and firmware designs, Quantum 
Digital also offers valueadded services including: 
    
SolidState Memory Card (No 
Moving Parts)   
Capacity: 128MB to 16GB   
CFA 4.1 and ATA7 Compatible   
ATA Transfer modes:   
  UDMA 06, MWDMA 04   
UDMA 06, MWDMA 02 
Supports True IDE and PC Card 
Memory and I/O Modes 
Form Factors:   
  Compact Flash Type I 
  Compact Flash Type II 
  Compact Flash Adapter 
Advanced WearLeveling for 
Greater Flash Endurance 
Card Information Structure (CIS) 
Programmed into Internal 
Memory 
PC Card and Socket Services 
Release 2.1 or later compatible 
5V or 3.3V Power Supply   
Commercial and Industrial 
Operating Temperature Ranges 
Available 
Full DataPath Protection with 
builtin ECC Engine   
10 Year Data Retention 
RoHS6 Compliant 
Free Datasheet http://www.0PDF.com







QDCF-8GUH1I pdf, 数据表
PRODUCT SPECIFICATION
QDCFxxx(M/G)UH1(I) 
                                                                                                                                                                          Datasheet
1.1. Scope
This document describes the features, specifications and installation guide of the Industrial CF Cards. In the appendix,
there provides order information, warranty policy, RMA/DOA procedure for the most convenient reference.
1.2. System Features
Optional Rugged metal Compact Flash casing to sustain the harshest environments
Non-volatile memory and no moving parts
SLC-NAND type flash technology
Card capacity from 16MB to 32GB
ATA interface and support PC Card Memory mode, PC Card I/O mode and True IDE mode
Data transfer supports PIO-4 and UDMA-4 (Default setting)
Performance up to 40 MB/sec
Automatic 4 bits error correction (ECC ) and retry capabilities
+5 V ±10or +3.3 V ±5operation
MTBF 3,000,000 hours.
Shock : 1,500G , compliance to MIL-STD-810F
Vibration : 15G, compliance to MIL-STD-810F
Support various rugged and harsh environments
Very high performance, very low power consumption
Low weight, Noiseless
Conformal coating upon special request
1.3. CFA 3.0 Specification
Industrial CF Card is fully compatible with the CFA 3.0 specification.
1.4. ATA/ATAPI-6 Standard
Industrial CF Card is compliant to ATA/ATAPI-6 and below version.
1.5. Technology Independence - Static Wear Leveling
In order to gain the best management for flash memory, the Industrial CF Card supports Static Wear Leveling technology
to manage the Flash system. The life of flash memory is limited; the management is to increase the life of the flash
product.
A static wear-leveling algorithm evenly distributes data over an entire Flash cell array and searches for the least used
physical blocks. The identified low cycled sectors are used to write the data to those locations. If blocks are empty, the
write occurs normally. If blocks contain static data, it moves that data to a more heavily used location before it moves the
newly written data. The static wear leveling maximizes effective endurance Flash array compared to no wear leveling or
dynamic wear leveling.
-2-
40000-CF-XXX-01AX, March 2011
Free Datasheet http://www.0PDF.com







QDCF-8GUH1I equivalent, schematic
PRODUCT SPECIFICATION
QDCFxxx(M/G)UH1(I) 
                                                                                                                                                                          Datasheet
Signal Name
-CSEL
(True IDE Mode)
D15 – D00
(PC Card Memory Mode)
D15 – D00
(PC Card I/O Mode)
D15 – D00
(True IDE Mode)
GND
(PC Card Memory Mode)
GND
(PC Card I/O Mode)
GND
(True IDE Mode)
-INPACK
(PC Card Memory Mode)
-INPACK
(PC Card I/O Mode)
Input Acknowledge
DMARQ
(True IDE Mode)
-IORD
(PC Card Memory Mode)
-IORD
(PC Card I/O Mode)
-IORD
(True IDE Mode –Except Ultra DMA
Protocol Active )
-HDMARDY
Dir Pin
Description
This internally pulled up signal is used to configure this device as a
Master or a Slave when configured in the True IDE Mode.
When the pin is open, this device is configured as a Slave.
I/O
31,30,29,28,2
7,49,48,47,6,
5,4,3,2,23,22,
21
These lines carry the Data, Commands and Status information
between the host and the controller. D00 is the LSB of the Even Byte
of the Word. D08 is the LSB of the Odd Byte of the Word.
This signal is the same as the PC Card Memory Mode signal.
In True IDE Mode, all Task File operations occur in byte mode on the
low order bus D[7:0] while all data transfers are 16 bit using D[15:0].
-- 1,50
Ground
This signal is the same for all modes.
This signal is the same for all modes.
O 43
I 34
This signal is not used in this mode.
The Input Acknowledge signal is asserted by the Compact Flash
Card or CF+ Card when the card is selected and responding to an
I/O read cycle at the address that is on the address bus. This signal
is used by the host to control the enable of any input data buffers
between the Compact Flash Card or CF+ Card and the CPU.
This signal is a DMA Request that is used for DMA data transfers
between host and device. It shall be asserted by the device when it is
ready to transfer data to or from the host. For Multiword DMA
transfers, the direction of data transfer is controlled by –IORD
and –IOWR. This signal is used in a handshake manner
with –DMACK, i.e., the device shall wait until the host
asserts –DMACK before negating DMARQ and re-asserting DMARQ
if there is more data to transfer.
DMAARQ shall not be driven when the device is not selected.
While a DMA operation is in progress, -CS0 and –CS1 shall be held
negated and the width of the transfers shall be 16bits.
If there is no hardware support for DMA mode in the host, this output
signal is not used and should not be connected at the host. In this
case, the BIOS must report that DMA mode is not supported by the
host so that device will not attempt DMA mode.
A host that does not support DMA mode and implements both
PCMCIA and True-IDE modes of operation need not alter the
PCMCIA mode connections while in True-IDE mode as long as this
does not prevent proper operation in any mode.
This signal is not used in this mode.
This is an I/O Read strobe generated by the host. This signal gates
I/O data onto the bus from the Compact Flash Card or CF+ Card
when the card is configured to use the I/O interface.
In True IDE Mode, while Ultra DMA mode is not active, this signal
has the same function as in PC Card I/O Mode.
In True IDE Mode when Ultra DMA mode DMA Read is active this
- 10 -
40000-CF-XXX-01AX, March 2011
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