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PDF ( 数据手册 , 数据表 ) JE310

零件编号 JE310
描述 (JE300 - JE360) JPEG Baseline Encoder IP-Core Users Manual
制造商 Penz VHDL
LOGO Penz VHDL LOGO 


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JE310 数据手册, 描述, 功能
Free Datasheet http://www.0PDF.com
JE300, JE310,
JE350 and JE360
JPEG Baseline Encoder IP-Core
Users Manual
Rev 3.0
© by Penz VHDL
Frankenstr. 16
D-55299 Nackenheim
Germany
www.penz-vhdl.de







JE310 pdf, 数据表
Penz VHDL
Free Datasheet http://www.0PDF.com
JE300, JE310, JE350 and JE360
1.6 Zigzag Order
The quantized coefficients of a block are rearranged in that way that there are sorted
from DC to the highest frequencies. The goal is to have a large number of
subsequent zeros for the following Run / Size encoding.
Figure 6: Zigzag Order from 8x8 Block
0 1 5 6 14 15 27 28
2 4 7 13 16 26 29 42
3 8 12 17 25 30 41 43
9 11 18 24 31 40 44 53
10 19 23 32 39 45 52 54
20 22 33 38 46 51 55 60
21 34 37 47 50 56 59 61
35 36 48 49 57 58 62 63
1.7 Differential DC Encoding
The DC coefficient represents the average value of all 64 samples. Because the
average differs only slightly from one block to the next, the DC coefficient is
differential encoded. From the DC coefficient, is subtracted the DC coefficient from
the previous block of the same component. For the first block in the image, is a
predicted value of zero defined. The difference is usually a short value and results so
in a short integer in the following symbol encoding.
8







JE310 equivalent, schematic
Penz VHDL
Free Datasheet http://www.0PDF.com
JE300, JE310, JE350 and JE360
4. The JE300, JE310, JE350 and JE360 JPEG Encoder
4.1 Technical Features
Optimized for Xilinx Spartan and Virtex FPGA
Marker generation included
JPEG file output
Baseline Encoder
Compliant with Baseline ISO/IEC 10918-1
Block building RAM included, no external RAM needed
Mono chrome or Color (YCbCr 4:2:2)
Up to 4096 pixel per row
Line by line pixel input
Motion-JPEG capability
8-bit/pixel or 12-bit/pixel input (Core dependent)
2 Quantization tables
4 fixed Huffman tables (2 DC and 2 AC)
Predefined luminance and chrominance tables
Fully synchronous design
Fully stall able design
Simple CPU interface for Quantization table reprogramming
Different clocks for encoder and CPU interface
Single clock cycle per pixel encoding
No pause cycles between blocks
4.2 Difference between JE300, JE310, JE350 and JE360
The four cores are very similar, but optimized for different FPGA families and input
sample precision:
Table 3: Difference between Cores
FPGA 8 Bit Sample 12 Bit Sample
Family Precision Precision
Spartan-II
Spartan-IIE
Virtex
JE300
JE350
Virtex-E
Spartan-III
Virtex-II
JE310
JE360
Virtex-IIP
16










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