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PDF ( 数据手册 , 数据表 ) OZ976

零件编号 OZ976
描述 (OZ972 / OZ976) Intelligent CCFL Inverter Controller
制造商 O2Micro
LOGO O2Micro LOGO 


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OZ976 数据手册, 描述, 功能
OZ972/OZ976
Change Summary
CHANGES
No. Applicable Section
1. Ordering Information
2. OZ972 Typical Application Circuit
3. Throughout data sheet
Description
a) Add OZ972GN, OZ972IGN, OZ976TN & OZ976ITN
Change C18 value from “0.1u” to “open”
Miscellaneous corrections
Page(s)
1
16
---
REVISION HISTORY
Revision No.
0.97
0.98
0.99
1.0
Description of change
Initial release
1. Revise part number in header and footer to read “OZ972/OZ976” and ensure text diagrams and figures are in this sequence throughout data
sheet; 2. Add alpha to part numbers in “Ordering Information”; 3. Add patent number in footer of first page; 4. Update the OZ972 and OZ976
functional block diagrams, application circuit figures and functional specifications; 5. Revise "Functional Specifications" for OZ972 and OZ976 as
follows: OZ972 - a) first test condition listed, b) add note (2), c) add note (2) to Input Offset Voltage and change Max. limit, d) add note (2) to Input
Voltage Range, Open Loop Voltage Gain and Unity Gain Bandwidth under Error Amplifier, e) delete Power Supply Rejection parameter, f) add
Source and Sink Current parameters [with note (2)] under Error Amplifier, g) add note (2) to NDR-PDR Output Resistance (current source) and
change Max. limit, h) add note (2) to NDR-PDR Output Resistance (current sink) and change Typ. & Max. limits, i) change Max./Min. Overlap title
to “Maximum Overlap”, j) Maximum Overlap between Diagonal Switches Min. & Typ. limits, k) delete Gate Drive (A,B,C,D) Off Condition
parameter, l) Break-Before-Make PDR_A/NDR_B and PDR_C/NDR_D Min. & Max. limits, m) OVP test condition, Min. and Typ. limits; OZ976 - n)
Add notes (4) & (5), o) add note (4) to Reference Voltage-Nominal and change Min., Typ. & Max. limits, p) add note (5) to Reference Voltage-Line
Regulation and change Max. limit, q) add note (5) to Reference Voltage-Load Regulation and change Max. limit, r) add Source and Sink Current
parameters under Reference Voltage, s) delete CT Oscillator Initial Accuracy parameter, t) add note (5) to CT Oscillator Ramp Peak and Valley
and change Min. & Max. limits, u) CT Oscillator CLK Frequency Min., Typ. & Max limits, v) LCT Oscillator Initial Accuracy Min., Typ. & Max limits,
w) add note (5) to LCT Oscillator Ramp Peak and Valley and change Min. & Max. limits, x) Threshold ENA Min. & Max. limits, y) change Threshold
VIN title to “Threshold VINS” and change Min. & Max. limits, and z) add TALK parameter under Threshold; 6. Correct subtitle under item “15.” to
0read “VINS”; 7. Update the formulas for the operation frequency (under item “16.”) and internal LCT frequency (under item “18.”); and 8. Misc.
corrections.
51. Features & Gen’l Description--correct application lamp numbers; 2. Correct package type in part name in Ordering Information; 3. Update
0Functional Block Diagram; 4. Update OZ976 Typical Application Circuit; 5. OZ976 Pin Description--delete note ref. for pin #’s 38, 44 & 45; 6.
Complete ‘Package Power Dissipation’ value in Absolute Max. Ratings; 7. OZ972 Functional Specs a) replace ‘Input voltage range‘ parameter &
2limits with ‘Reference voltage at non-inverting input pin (internal)’ parameter & limits, b) correct ‘Max. Overlap between diagonal switches’ test
condition, c) correct Break-Before-Make ‘PDR_A/NDR_B’ test conditions, Typ & Max limits, and ‘PDR_C/NDR_D test conditions, Min & Max limits,
rd) correct ‘OVP’ Min, Typ & Max limits, e) correct ‘Supply Current’ test conditions, Typ & Max limits, f) correct ‘Supply current’ test conditions, Typ
e& Max limits, and g) ‘SST current’ Min, Typ & Max limits; 8. OZ976 Functional Specs a) add note (5) to CT Oscillator ‘Temp. stability’, and b)
correct ‘Supply Current’ test conditions; 9. Functional Description, 7, 6th line, correct voltage referenced; 10. Functional Description, 8, 1st line,
bcorrect voltage referenced; 11. Functional Description, correct voltage referenced in last line; 12. Functional Description, 18, correct Internal LCT
frequency formula; 13. Package Information, delete symbol ‘C’ in table; not included in the drawing; and 14. Misc. corrections.
m1. Add OZ972IG & OZ976IT packages and table that include temp range of each package in Ordering Information and General Description, 2.
Delete “I/O” columns in Pin Description tables, 3.Absolute Max. Ratings a) Modify table title, b) move note “(1)” from “VDDA, VDDA2, VDDD, VDD”
uto the table title, c) change “Logic Inputs” to read “Signal Inputs”, d) revise Resonator Frequency’, and e) add separate Operating Temp. table that
breaks out commercial and industrial temp ranges, 4. OZ972 Electrical Characteristics Revise a) table title, b) add temp range before the table, c)
Nfirst test condition at beginning of table, d) delete ‘Input offset voltage’ parameter, e) add test conditions and Min, Typ & Max limits for ‘Reference
lvoltage at non-inverting input pin’ and revise current Min, Typ & Max limits, f) delete ‘Open loop voltage gain’ and Unity gain bandwidth’
parameters, g) change ‘Source Current’ title to read ‘Output voltage’, add symbol and test condition, and revise Min, Typ, Max limits & units, h)
riadelete ‘Sink Current’ parameter, i) test conditions for ‘NDR-PDR Output’ parameters, adding Min, Typ, Max limits & units for new test conditions, j)
‘Break-Before-Make’ parameters Min, Typ & Max limits, k) add test condition plus Min, Typ, Max limits & unit to ‘Threshold OVP’ and update
current test conditions, Min, Typ & Max limits, and add ‘Talk’ parameter, l) ‘Supply current (ON)’ test conditions, m) ‘SST current Min, Typ & Max
elimits, and n) add ‘CTIMR current’ test conditions, adding Min, Typ, Max limits & units for new test conditions, and revising current Min, Typ & Max
limits, 5. OZ976 Electrical Characteristics Revise a) table title, b) add temp range before the table, c) first test condition at beginning of table, d)
Sadd ‘Nominal voltage’ test conditions, adding Min, Typ, Max limits & units for new test conditions, and revising current Min, Typ & Max limits, e)
‘Line regulation’ note numbers and Max limit, f) delete ‘Load regulation’, ‘Source Current’ and ‘Sink Current’, g) add test condition plus Min, Typ,
Max limits & unit to ‘CLK Frequency’ and update current test conditions, Min, Typ & Max limits, h) add test condition plus Min, Typ, Max limits &
unit to ‘Initial Accuracy’ and update current test conditions, Min, Typ & Max limits, i) delete ‘Ramp peak/valley’ parameters, j) add note (3) to ‘Low
Frequency PWM’, k) add symbol and test conditions (9) plus Min, Typ, Max limits & units to ‘Duty Cycle Range’ and update current Max limit, l)
’Threshold’ parameter names, deleting ‘ENA’ and VINS’, and all limits, m) add note (5) to ‘Talk’ parameter, n) ‘Supply current (low)’ Max lilmit, o)
‘Supply current (high)’ test condition and Max limit, and p) note (3), 6. OZ972 & OZ976 Functional Block Diagrams a) Revise ENA non-inverting
node voltage, SST current, and OVP threshold voltage, and b) delete phase shift in OZ976 diagram, 7. Functional Description a) Item 7., revise
voltage in line 6, b) Item 8., revise OVP threshold voltage in line 1, c) Item 11., revise non-inverting voltage in last line, and d) Item 18., update
formula, 8. Change C116 value to 33p in OZ976 Typical Application Circuit, 9. Add part numbers to titles of Package Information & 10. Misc.
Release
Date
10/21/02
04/23/03
05/13/03
01/27/04
OZ972/OZ976-DS-1.1
Page 0
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OZ976 pdf, 数据表
OZ972/OZ976
OZ976 ELECTRICAL CHARACTERISTICS (CONTINUED)
OZ976: 0oC < Tamb < 70oC, unless otherwise specified
OZ976I: -40oC < Tamb < 85oC, unless otherwise specified
Parameter
Symbol
Test Conditions
VDDA/VDDA2/VDDD = 5V;
unless otherwise specified
Limits
Min Typ Max
Unit
Threshold
ENABLE
DISABLE
ENA
2.0 -
-
- - 1.0
V
V
VINS (ON)
1.65 - - V
VINS (OFF)
- - 1.25 V
TALK(5)
Logic High
Logic Low
3.5 -
-
V
- - 1.6
Supply
Supply current
ENA = low
- 165 280 µA
ENA = high
12-phase selection
Supply current
-
4.4 5.5
mA
VDIM = 2V; L0-L11 = 50k(3)
CLK = 63kHz; LCT = 210Hz
Notes:
(1) CT: capacitor from CT (pin 34) to ground
RT: resistor from RT (pin 41) to ground
r(2) LCT: capacitor from LCT (Pin 43) to ground
eRT: resistor from RT (pin 41) to ground
b(3) L0-L11: 50kresistor is connected from L0-L11 (Pins 14-23 and 27-28) to ground
A 4MHz resonator is connected to OSCA and OSCY
m(4) Reference voltage measured when CT, CLK, LCT & resonator are not active.
Serial Nu(5) Denotes that parameter is guaranteed by design and not production tested.
2050
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OZ976 equivalent, schematic
OZ972/OZ976
ENA_PP
The OZ976 ENA_PP pin connects to all ENAs of
OZ972. When VINS, ENA, IND and TALK are
satisfied, ENA_PP goes high to enable the
operation of the OZ972s. The system will be
disabled when VINS is in an under-voltage lock
out condition or ENA is low. In addition, when
TALK has a falling edge with IND set low,
ENA_PP goes low and disables the system. In
this condition, only when VINS and ENA are
satisfied, toggling VDDA will resume system
operation.
16. Operation Frequency
fLCT[Hz] =
102103
CLCT[nF]RT[k]
The peak and valley of the LCT signal is
nominally 3V and 1V respectively. The VDIM
signal is compared to the triangle wave in LCT
and yields a proper pulse width to modulate the
CCFL current. By programming POL, the positive
or negative pulse width will be duplicated and
imposed on the PWM signal. The designer
defines the relationship between VDIM and panel
brightness. Setting POL high, an increase in
VDIM, will increase the panel brightness.
Conversely, setting POL low, a decrease in
VDIM, will increase the panel brightness.
A resistor RT and capacitor CT determine the
operating frequency of the OZ976. The frequency
is calculated as follows:
PWM Frequency
Through VSYNC, PWM signals can be
synchronized with an external control signal with
fCLK[KHz] =
675103
CT[pF]RT[k]
a TTL level frequency range from 65Hz to 180Hz.
If a VSYNC signal does not exist, the OZ976
uses the LCT signal to synchronize the PWM
The OZ976 also provides an optional striking
frequency if desired. When RT1 is used, it is
connected in parallel with RT during the ignition
period, and provides a higher frequency for
0striking. After enable, OZ976 detects TALK pin’s
5first rising edge and RT1 is disconnected.
20CT is a saw-tooth waveform and its frequency is
rdouble the fCLK operation frequency. CLK is a
esquare waveform and its frequency is the
operation frequency. Both of these signals are
bused by the OZ972 to control the output drivers,
mPDR_A, NDR_B, PDR_C and NDR_D.
Nu17. Reference Voltage
rialOZ976 is the voltage source providing all OZ972
the reference voltage through REF pin. All
OZ972s follow the REF voltage and generate
einternal references. The reference voltage is
Sactivated approximately 1ms before ENA_PP
signals. All PWM signals are synchronized with
either the internal (LCT) or external (VSYNC)
signal. The PWM signals are twice the frequency
of the internal or external signal.
PWM Dimming Signals
The PWM dimming signal frequency is extracted
from either an internal LCT signal or from the
external VSYNC signal. The pulse width of PWM
dimming signal comes from the comparison
result of LCT and VDIM. There is a fixed phase
delay between sequential PWM dimming signals.
The PWM Generator generates a new set of
PWM dimming signals resulting from the
combination of Pulse Width, X2 PWM dimming
frequency and Phase Delay. All PWM signals
have the same pulse width and frequency. The
only difference among the PWM signals is the
phase delay, which is determined by the PWM
dimming period divided by the number of phases.
No two PWM signals have the same phase shift
amount.
goes high and it lasts 1ms after ENA_PP goes
low. The time delay relates to the resonator
frequency of OSCA and OSCY.
SEL0 and SEL1
The SEL0 and SEL1 pins are used to select the
number of lamps, from 6, 8, 10 and 12.
18. PWM Dimming Control
Table 1. OZ976 Phase Select Logic
OZ976 provides PWM dimming signals to each
OZ972 with an equal phase delay.
SEL0
0
SEL1
0
No. of Phases
6
Internal LCT Frequency
The internal pre-programmed PWM frequency T1
(see Case 2, page 23) is determined by a
01
10
11
8
10
12
capacitor connected to the LCT pin. An
approximation of the frequency can be calculated
by:
L0 to L11
L0 to L11 are the PWM signal output pins. All of
the outputs are a 3-state buffer.
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