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PDF ( 数据手册 , 数据表 ) HI-548

零件编号 HI-548
描述 Single 16 and 8/ Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection
制造商 Intersil Corporation
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HI-548 数据手册, 描述, 功能
Data Sheet
HI-546, HI-547, HI-548, HI-549
June 1999 File Number 3150.2
Single 16 and 8, Differential 8-Channel
and 4-Channel CMOS Analog MUXs with
Active Overvoltage Protection
The HI-546, HI-547, HI-548 and HI-549 are analog
multiplexers with active overvoltage protection and
guaranteed rON matching. Analog input levels may greatly
exceed either power supply without damaging the device or
disturbing the signal path of other channels. Active
protection circuitry assures that signal fidelity is maintained
even under fault conditions that would destroy other
multiplexers.
Analog inputs can withstand constant 70VP-P levels with
±15V supplies. Digital inputs will also sustain continuous
faults up to 4V greater than either supply. In addition, signal
sources are protected from short circuiting should
multiplexer supply loss occur. Each input presents 1kof
resistance under this condition. These features make the
HI-546, HI-547, HI-548 and HI-549 ideal for use in systems
where the analog inputs originate from external equipment
or separately powered circuitry. All devices are fabricated
with 44V Dielectrically Isolated CMOS technology. The
HI-546 is a single 16-Channel, the HI-547 is an 8-Channel
differential, the HI-548 is a single 8-Channel and the HI-549
is a 4-Channel differential device. If input overvoltage
protection is not needed the HI-506/507/508/509
multiplexers are recommended. For further information see
Application Notes AN520 and AN521.
For MIL-STD-883 compliant parts, request the HI-546/883,
HI-547/883, HI-548/883 and HI-549/883 datasheets.
Features
• Analog Overvoltage Protection. . . . . . . . . . . . . . . . . . 70VP-P
• No Channel Interaction During Overvoltage
• Guaranteed rON Matching
• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . . 44V
• Break-Before-Make Switching
• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 500ns
• Standby Power (Typical) . . . . . . . . . . . . . . . . . . . . . 7.5mW
Applications
• Data Acquisition
• Industrial Controls
• Telemetry
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HI1-0546-5
0 to 75 28 Ld CERDIP
HI1-0546-2
-55 to 125 28 Ld CERDIP
HI3-0546-5
0 to 75 28 Ld PDIP
HI4P0546-5
0 to 75 28 Ld PLCC
HI9P0546-9
-40 to 85 28 Ld SOIC
HI1-0547-5
0 to 75 28 Ld CERDIP
HI3-0547-5
0 to 75 28 Ld PDIP
HI4P0547-5
0 to 75 28 Ld PLCC
HI9P0547-9
-40 to 85 28 Ld SOIC
HI1-0548-2
-55 to 125 16 Ld CERDIP
HI1-0548-5
0 to 75 16 Ld CERDIP
HI3-0548-5
0 to 75 16 Ld PDIP
HI4P0548-5
0 to 75 20 Ld PLCC
HI9P0548-5
0 to 75 16 Ld SOIC
HI9P0548-9
-40 to 85 16 Ld SOIC
HI1-0549-2
-55 to 125 16 Ld CERDIP
HI3-0549-5
0 to 75 16 Ld PDIP
HI4P0549-5
0 to 75 20 Ld PLCC
HI9P0549-5
0 to 75 16 Ld SOIC
HI9P0549-9
-40 to 85 16 Ld SOIC
PKG.
NO.
F28.6
F28.6
E28.6
N28.45
M28.3
F28.6
E28.6
N28.45
M28.3
F16.3
F16.3
E16.3
N20.35
M16.15
M16.15
F16.3
E16.3
N20.35
M16.15
M16.15
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999







HI-548 pdf, 数据表
HI-546, HI-547, HI-548, HI-549
Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless
Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued)
PARAMETER
TEST
CONDITIONS
TEMP
(oC)
MIN
-2
TYP MAX
-5, -9
MIN TYP MAX UNITS
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, VIN
On Resistance, rON
Note 2
Full -15 - +15 -15 - +15 V
25 - 1.2 1.5 - 1.5 1.8 k
Full - 1.5 1.8 - 1.8 2.0 k
rON, (Any Two Channels)
Off Input Leakage Current, IS(OFF)
Note 3
25 -
- 7.0 -
- 7.0 %
25 - 0.03 -
- 0.03 -
nA
Full -
- 50 -
- 50 nA
Off Output Leakage Current, ID(OFF)
HI-546
Note 3
25 - 0.1 -
- 0.1 - nA
Full -
- 300 -
- 300 nA
HI-547
Full -
- 200 -
- 200 nA
HI-548
Full -
- 200 -
- 200 nA
HI-549
Full -
- 100 -
- 100 nA
ID(OFF) With Input Overvoltage Applied Note 4
25 - 4.0 -
- 4.0 - nA
Full - - 2.0 - - - µA
On Channel Leakage Current, ID(ON)
HI-546
Note 3
25 - 0.1 -
- 0.1 - nA
Full -
- 300 -
- 300 nA
HI-547
Full -
- 200 -
- 200 nA
HI-548
Full -
- 200 -
- 200 nA
HI-549
Full -
- 100 -
- 100 nA
Differential Off Output Leakage Current
IDIFF (HI-547, HI-549 Only)
POWER SUPPLY CHARACTERISTICS
Full -
- 50 -
- 50 nA
Power Dissipation, PD
Current, I+
Note 7
Full - 7.5 -
- 7.5 - mW
Full - 0.5 2.0 - 0.5 2.0 mA
Current, I-
Note 7
Full
- 0.02 1.0
-
0.02 1.0
mA
NOTES:
2. VOUT = ±10V, IOUT = 100µA.
3. 10nA is the practical lower limit for high speed measurement in the production test environments.
4. Analog Overvoltage = ±33V.
5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC.
6. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS, f = 100kHz.
7. VEN, VA = 0V or 4V.
8. To drive from DTL/TTLCircuits, 1kpull-up resistors to +5V supply are recommended.
8














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