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零件编号 | P45N02LDG | ||
描述 | N-Channel Logic Level Enhancement Mode Field Effect Transistor | ||
制造商 | Niko-Sem | ||
LOGO | |||
1 Page
NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P45N02LDG
TO-252 (DPAK)
Lead-Free
PRODUCT SUMMARY
V(BR)DSS
RDS(ON)
25 20m
ID
45A
D
G
S
1. GATE
2. DRAIN
3. SOURCE
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current1
TC = 25 °C
TC = 100 °C
Avalanche Current
Avalanche Energy
Repetitive Avalanche Energy2
L = 0.1mH
L = 0.05mH
Power Dissipation
TC = 25 °C
TC = 100 °C
Operating Junction & Storage Temperature Range
Lead Temperature (1/16” from case for 10 sec.)
VGS
ID
IDM
IAR
EAS
EAR
PD
Tj, Tstg
TL
LIMITS
±20
45
28
140
20
140
5.6
55
33
-55 to 150
275
UNITS
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
Junction-to-Case
RθJC
Junction-to-Ambient
RθJA
Case-to-Heatsink
RθCS
1Pulse width limited by maximum junction temperature.
2Duty cycle ≤ 1
TYPICAL
0.7
MAXIMUM
3
70
UNITS
°C / W
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current1
V(BR)DSS
VGS(th)
IGSS
IDSS
ID(ON)
STATIC
VGS = 0V, ID = 250µA
VDS = VGS, ID = 250µA
VDS = 0V, VGS = ±20V
VDS = 20V, VGS = 0V
VDS = 20V, VGS = 0V, TJ = 125 °C
VDS = 10V, VGS = 10V
LIMITS
UNIT
MIN TYP MAX
25
0.8 1.2
2.5
V
±250 nA
25
µA
250
45 A
1 Sep-02-2004
Free Datasheet http://www.datasheet-pdf.com/
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页数 | 5 页 | ||
下载 | [ P45N02LDG.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
P45N02LD | N-Channel Logic Level Enhancement Mode Field Effect Transistor | Niko-Sem |
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P45N02LDG | N-Channel Logic Level Enhancement Mode Field Effect Transistor | Niko-Sem |
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