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PDF ( 数据手册 , 数据表 ) ST24LC21B

零件编号 ST24LC21B
描述 (ST24xx21B) 1 Kbit x8 Dual Mode Serial EEPROM
制造商 STMicroelectronics
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ST24LC21B 数据手册, 描述, 功能
ST24LC21B, ST24LW21
ST24FC21, ST24FC21B, ST24FW21
1 Kbit (x8) Dual Mode Serial EEPROM
for VESA PLUG & PLAY
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
3.6V to 5.5V or 2.5V to 5.5V SINGLE SUPPLY
VOLTAGE
HARDWARE WRITE CONTROL (ST24LW21
and ST24FW21)
TTL SCHMITT-TRIGGER on VCLK INPUT
100k / 400k Hz COMPATIBILITY with the I2C
BUS BIT TRANSFER RANGE
TWO WIRE SERIAL INTERFACE I2C BUS
COMPATIBLE
I2C PAGE WRITE (up to 8 Bytes)
I2C BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ERROR RECOVERY MECHANISM
(ST24FC21 and ST24FW21) VESA 2
COMPATIBLE
DESCRIPTION
The ST24LC21B, ST24LW21, ST24FC21,
ST24FC21B and ST24FW21 are 1K bit electrically
erasable programmable memory (EEPROM), or-
ganized in 128x8 bits. In the text, products are
referred as ST24xy21, where "x" is either "L" for
VESA 1 or "F" for VESA 2 compatible memories
and where "y" indicates the Write Control pin con-
nection: "C" means WC on pin 7 and "W" means
WC on pin 3.
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
VCC
SCL
VCLK
WC
ST24xy21
SDA
Table 1. Signal Names
SDA
SCL
Serial Data Address Input/Output
Serial Clock (I2C mode)
VCC
VSS
VCLK
Supply Voltage
Ground
Clock Transmit only mode
WC Write Control
June 2002
VSS
AI01741
Note: WC signal is only available for ST24LW21 and ST24FW21
products.
1/22
Free Datasheet http://www.datasheet4u.net/







ST24LC21B pdf, 数据表
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )
Symbol
Parameter
Test Condition
CIN Input Capacitance (SDA)
CIN Input Capacitance (other pins)
tLP
Low-pass filter input time constant
(SDA and SCL)
Note: 1. Sampled only, not 100% tested.
Min Max Unit
8 pF
6 pF
200 500
ns
Table 6A. DC Characteristics (ST24LC21B, ST24LW21, ST24FC21 and ST24FW21)
(TA = –40 to 85 °C; VCC = 3.6V to 5.5V)
Symbol
Parameter
Test Condition
Min Max
ILI Input Leakage Current
ILO Output Leakage Current
0V VIN VCC
0V VOUT VCC
SDA in Hi-Z
±2
±2
Supply Current
ICC
Supply Current
ICC1 Supply Current (Standby)
ICC2 Supply Current (Standby)
VIL
Input Low Voltage
(SCL, SDA, WC)
VCC = 5V, fC = 400kHz
(Rise/Fall time < 10ns)
VCC = 3.6V, fC = 400kHz
VIN = VSS or VCC,
VCC = 5V, fC = 0
VIN = VSS or VCC,
VCC = 5V, fC = 400kHz
VIN = VSS or VCC,
VCC = 3.6V, fC = 0
VIN = VSS or VCC,
VCC = 3.6V, fC = 400kHz
–0.3
2
1
100
300
30
100
0.3 VCC
VIH
Input High Voltage
(SCL, SDA, WC)
0.7 VCC
VCC + 1
VP
High Level Threshold Voltage
(Schmitt Trigger on VLCK)
VN
Low Level Threshold Voltage
(Schmitt Trigger on VLCK)
VH
Hysteresis Voltage
(Schmitt Trigger on VLCK)
VOL Output Low Voltage
VCC = 5.5V
VCC = 4.5V
VCC = 3.6V
VCC = 5.5V
VCC = 4.5V
VCC = 3.6V
VCC = 5.5V
VCC = 4.5V
VCC = 3.6V
IOL = 3mA, VCC = 3.6V
IOL = 6mA, VCC = 5V
1.4
1.2
1
0.6
0.5
0.4
0.4
0.4
0.35
2.1
1.9
1.7
1.4
1.2
1
1.5
1.4
1.3
0.4
0.6
Unit
µA
µA
mA
mA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
V
V
V
8/22
Free Datasheet http://www.datasheet4u.net/







ST24LC21B equivalent, schematic
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 12. Inhibited Write when VCLK/WC = 0
VCLK/WC
BYTE WRITE
PAGE WRITE
CONTROL
BYTE
ACK
ACK
WORD ADDR
DATA
ACK
CONTROL
BYTE
ACK
ACK
ACK
ACK
WORD ADD n
DATA n
DATA n + 1 DATA n + 7
ACK
AI01894
– Step 1: the Master issues a START condition
followed by a Device Select byte (1st byte of
the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond with an ACK, indicating that the mem-
ory is ready to receive the second part of the
instruction (the first byte of this instruction was
already sent during Step 1).
Read Operations
On delivery, the memory content is set at all "1’s"
(or FFh).
Current Address Read. The memory has an inter-
nal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends the Device Select code with the
RW bit set to ’1’. The memory acknowledges this
and outputs the data byte addressed by the internal
byte address counter. This counter is then incre-
mented. The master must NOT acknowledge the
data byte output and terminates the transfer with a
STOP condition.
Random Address Read. A dummy write is per-
formed to load the address into the address
counter, see Figure 14. This is followed by a Re-
START condition send by the master and the De-
vice Select code is repeated with the RW bit set to
’1’. The memory acknowledges this and outputs the
addressed data byte. The master must NOT ac-
knowledge the data byte output and terminates the
transfer with a STOP condition.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last data byte
output, and MUST generate a STOP condition.
The output data is from consecutive byte ad-
dresses, with the internal byte address counter
automatically incremented after each byte output.
After a count of the last memory address, the
address counter will ’roll-over’ and the memory will
continue to output data.
Acknowledge in Read Mode. In all read modes
the ST24xy21 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
16/22
Free Datasheet http://www.datasheet4u.net/










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