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PDF ( 数据手册 , 数据表 ) TC58NVG6T2FTA00

零件编号 TC58NVG6T2FTA00
描述 64 GBIT (8G X 8 BIT) CMOS NAND E2PROM
制造商 Toshiba
LOGO Toshiba LOGO 


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TC58NVG6T2FTA00 数据手册, 描述, 功能
TOSHIBA CONFIDENTIAL TC58NVG6T2FTA00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
64 GBIT (8G 8 BIT) CMOS NAND E2PROM (Triple-Level-Cell)
DESCRIPTION
The TC58NVG6T2FTA00 is a single 3.3 V 64 Gbit (79,054,700,544 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (8192 1024) bytes 258 pages 4156 blocks.
The device has four 9216-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 9216-byte increments. The Erase operation is implemented in a single block
unit (2064 Kbytes 258 Kbytes:9216 bytes x 258 pages).
The TC58NVG6T2FTA00 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell array
Register
Page size
Block size
TC58NVG6T2FTA00
9216 1047.1171875K 8
9216 8
9216 bytes
(2064K 258K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read,
Multi Page Program, Multi Block Erase, Multi Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 4000 blocks
Max 4156 blocks
Power supply
VCC 2.7 V to 3.6 V
Access time
Cell array to register 110 s max
Serial Read Cycle
25 ns min
Program/Erase time
Auto Page Program
Auto Block Erase
2000 s/page typ.
3 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
50 mA max.
50mA max.
50 mA max.
100 A max
Package
TSOP I 48-P-1220-0.50C (Weight: 0.53 g typ.)
FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (15).
60 bit ECC for each 1K bytes is required.
1 2010-12-27C
Free Datasheet http://www.datasheet.in/







TC58NVG6T2FTA00 pdf, 数据表
TOSHIBA CONFIDENTIAL TC58NVG6T2FTA00
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of WE while ALE is High.
Chip Enable: CE
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The
CE signal is ignored when device is in Busy state ( RY / BY L), such as during a Program or Erase or Read
operation, and will not enter Standby mode even if the CE input goes High.
Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy: RY / BY
The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is
in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vcc with an appropriate resister.
Power on Select: PSL
The PSL signal is used to select whether the device initialization should take place during the device power
on or during the first Reset. Please refer to the application note (2) for details.
26
2010-12-27C
Free Datasheet http://www.datasheet.in/







TC58NVG6T2FTA00 equivalent, schematic
Package Dimensions
TOSHIBA CONFIDENTIAL
TC58NVG6T2FTA00
Weight: 0.53 g (typ.)
60
2010-12-27C
Free Datasheet http://www.datasheet.in/










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