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PDF ( 数据手册 , 数据表 ) WM8259

零件编号 WM8259
描述 Single Channel 16-Bit CIS/CCD AFE
制造商 Wolfson
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WM8259 数据手册, 描述, 功能
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WM8259
Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output
DESCRIPTION
The WM8259 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 3MSPS.
The device has two selectable video input pins and one
complete analogue signal processing channel containing
Reset Level Clamping, Correlated Double Sampling,
Programmable Gain and Offset adjust functions. Internal
multiplexers allow fast switching of offset and gain for line-
by-line colour processing. The output from this channel is
time multiplexed into a high-speed 16-bit Analogue to Digital
Converter. The digital output data is available in 4-bit wide
multiplexed format.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
The device uses an analogue supply voltage of 3.3V and a
digital interface supply of between 2.5V and 3.3V. The
WM8259 typically only consumes 132mW when operating
from a single 3.3V supply.
BLOCK DIAGRAM
FEATURES
16-bit ADC
3MSPS conversion rate
Low power - 132mW typical
3.3V single supply or 3.3V/2.5V dual supply operation
Single channel operation, selectable inputs
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
4-bit wide multiplexed data output format
Internally generated voltage references
20-lead SSOP package
Serial control interface
APPLICATIONS
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
WOLFSON MICROELECTRONICS plc
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Production Data, April 2007, Rev 4.2
Copyright ©2007 Wolfson Microelectronics plc







WM8259 pdf, 数据表
WM8259
INPUT VIDEO SAMPLING
t
PER
tt
MCLKH MCLKL
MCLK
VSMP
INPUT
VIDEO
t
VSMPSU
t
VSMPH
t
VSU
t
VH
Production Data
t
VPER
t
RSU
t
RH
Figure 1 Input Video Timing
Note:
1. See Page 15 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 18MHz unless otherwise stated.
PARAMETER
MCLK period
SYMBOL
tPER
TEST CONDITIONS
MIN
55.5
MCLK high period
tMCLKH
25
MCLK low period
tMCLKL
25
VSMP period
tVPER
300
VSMP set-up time
tVSMPSU
6
VSMP hold time
tVSMPH
3
Video level set-up time
tVSU
10
Video level hold time
tVH
3
Reset level set-up time
tRSU
10
Reset level hold time
tRH
3
Notes:
1. tVSU and tRSU denote the set-up time required after the input video signal has settled.
2. Parameters are measured at 50% of the rising/falling edge.
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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PD Rev 4.2 April 2007
8







WM8259 equivalent, schematic
WM8259
Production Data
PROGRAMMABLE VSMP DETECT CIRCUIT
The VSMP input is used to determine the sampling point and frequency of the WM8259. Under
normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling
frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on
the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal
may not be readily available. The programmable VSMP detect circuit in the WM8259 allows the
sampling point to be derived from any signal of the correct frequency, such as a CCD shift register
clock, when applied to the VSMP pin.
When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge
(determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse.
This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits.
Figure 13 shows the internal VSMP pulses that can be generated by this circuit for a typical clock
input signal. The internal VSMP pulse is then applied to the timing control block in place of the
normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising
MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.
INPUT
PINS
MCLK
VSMP
POSNNEG = 1
(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
VS VS VS
VS VS VS
VS VS VS
VS VS VS
VS VS VS
VS VS VS
VS VS VS
VS VS VS
POSNNEG = 0
(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
VS VS VS
VS VS VS
VS VS VS
VS VS VS
VS VS VS
VS VS VS
VS VS VS
VS VS VS
Figure 13 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
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PD Rev 4.2 April 2007
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