DataSheet8.cn


PDF ( 数据手册 , 数据表 ) QN8035

零件编号 QN8035
描述 Single-Chip Low-Power FM Receiver
制造商 Quintic
LOGO Quintic LOGO 


1 Page

No Preview Available !

QN8035 数据手册, 描述, 功能
QN8035
Single-Chip Low-Power FM Receiver for Portable Devices
Preliminary
________ General Description ________ _________Typical Applications________
The QN8035 is a high performance, low power; full-
featured single-chip stereo FM receiver designed for cell
phones, MP3 players. The QN8035 also supports
RDS/RBDS data reception.
Cell Phones / PDAs / Smart Phones
Portable Audio & Media Players
MP3/MP4 player, PMP, PND
_______________________________ Key Features ___________________________
Worldwide FM Band Coverage
60 MHz to 108 MHz full band tuning in
50/100/200 kHz step sizes
50/75µs de-emphasis
Ease of Integration
Small footprint, available in 2.5 x2.5 QFN16 and
3x3 MSOP10 packages
32.768 kHz and multiple MHz clocks input
I2C control interface
Very Low Power Consumption
13 mA typical
VCC: 2.7~5.0V, indegrated LDO, support battery
direct connection
Power saving Standby mode
Low shutdown leakage current
Accommodate 1.6~3.6V digital interface
Adaptive Noise Cancellation
Volume Control
High Performance
Superior sensitivity, better than 1.5 µVEMF
63dB stereo SNR, 0.03% THD
Integrated adaptive noise cancellation (SNC, HCC,
SM)
Improved auto channel seek
L/R separation 45dB
RDS/RBDS
1. Supports US and European data services
Superior sensitivity, better than 8.9 µVEMF
Robust Operation
-250C to +850C operation
ESD protection on all input and output pads
QN8035 Functional Blocks:
RX ANT
RFI
2.7–5.0V VCC
10µF
Voltage
Regulator
Tune
De
Mod
De
MPX
De
Emph
ARO
ALO
RDS
PHY
DSP FSM
Control Interface
XCLK
Ordering Information appears at Section 7.
SDA
SCL
I2C Controller
INT
Rev 0.08 (02/10)
Copyright ©2010 by Quintic Corporation
Page 1
Confidential A
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice..
Free Datasheet http://www.datasheet4u.com/







QN8035 pdf, 数据表
QN8035
Table 7: Timing Characteristics
(Typical values are at Vcc = 3.3V and TA = 25oC).
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNIT
τpup
Chip power-up time 1
From rising edge of CEN to
valid audio output.
TMOUT [1:0] = 00
τastby Auto Standby time 2 TMOUT [1:0] = 01
TMOUT [1:0] = 10
TMOUT [1:0] = 11
τchsw
Channel switching
time1
From any channel to any
channel.
1
3
5
Never
0.6
0.12
Sec
Min
Sec
Receiver Timing
τwkup
Wake-up time from
standby to receive
Standby to RX mode.
200 ms
τtune Tune time
Per channel during CCA.
5 ms
Notes:
1. Guaranteed by design.
2. Chip automatically goes from IDLE to standby mode; TMOUT = 11 equivalent to auto standby disabled.
Table 8: I2C Interface Timing Characteristics
(Typical values are at Vcc = 3.3V and TA = 25oC).
SYMBOL
fSCL
tLOW
tHI
tST
tSTHD
trc
tfc
tdtHD
tdtc
tstp
tw
Cb
PARAMETER
I2C clock frequency
Clock Low time
Clock High time
SCL input to SDA
falling edge start 1,3
SDA falling edge to
SCL falling edge start3
SCL rising edge3
SCL falling edge3
SCL falling edge to
next SDA rising edge3
SDA rising edge to
next SCL rising edge3
SCL rising edge to
SDA rising edge 2,3
Duration before restart3
SCL, SDA capacitive
CONDITIONS
Level from 30% to 70%
Level from 70% to 30%
MIN
1.3
0.6
0.8
0.8
20
0.6
1.3
TYP
MAX
400
UNIT
kHz
µs
µs
µs
µs
300 ns
300 ns
ns
900 ns
µs
µs
10 pF
Rev 0.08 (02/10)
Copyright ©2010 by Quintic Corporation
Page 8
Confidential A
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice.
Free Datasheet http://www.datasheet4u.com/







QN8035 equivalent, schematic
QN8035
50 kHz steps. The channel index and RF frequency have the enabled by RDS_INT_EN, RDS data buffer (Reg0Bh to
following relationship:
Reg12h) will be filled.
FRF = (60 + 0.05 x Channel Index), where FRF is the
RF frequency in MHz.
For example: To set the receiver to 106.9MHz, the channel
index can be calculated with the upper formula as shown
in following:
Channel index =(106.9-60)/0.05
=938
This translates into a hex number 0x3AA. So write 0xAA
to Reg07h [7:0] and write 0x03 to Reg0Ah[1:0] to tune to
the desired channel.
The results of error check-sum on four RDS blocks are
then available in STATUS2[3:0] (Reg13h[3:0]). If any
check-sum bit is non-zero, the corresponding RDS block is
not valid. Check the register map for detailed definition of
STATUS2[3:0].
E_DET bit (Reg13h[6]) is used for distinguishing whether
the received RDS group contains E (MMBS) block, and
RDSC0C1 (Reg13h[5]) bit is used for judging whether the
received group is A group or B group.
5.13 Programming Guide
Auto Seek
After setting start frequency, stop frequency, searching
step and search threshold, the auto seek function can be
enabled by setting CHSC (Reg00h [1]) to one. (Refer to
section 5.13-3 for programming guide).
Also, auto-seek supports a hardware interrupt function.
Refer to section 5.11 for more descriptions.
5.11 Hardware Interrupt
1) System Initialization:
To initialize the device, the following steps need to be
executed.
a. After powering up, execute software reset to the
QN8035.
b. Select injection clock type (sine-wave or digital-wave),
and set Reg01h[7].
The QN8035 supports a hardware interrupt function. It can
generate an interrupt signal to a MCU during auto seek or
RDS reception, in order to relieve the MCU from
continuous polling on the QN8035’s registers.
4.55ms
INT
c. Select clock frequency (32.768 KHz or other
frequencies), then set XTAL_DLV[10:0] (Reg15h to
Reg16h).
d. Set PLL_DLT[12:0] and write the computed result to
Reg16h[7:3] and Reg17h. For detailed configuration,
refer to section 5.3.
Figure 12 Interrupt Output
e. Software initialization. Refer to QN8035 application
note.
2) Manual Channel Tuning
If RDS_INT_EN (Reg17h[7])) is set to high, a low pulse of
roughly 4.55ms will be produced on the INT pin when a
new group of data is received and stored into RDS registers
in RDS mode.
Similarly, in CCA mode, after CCA_INT_EN (Reg17h[6])
is set to high, the same low pulse will be generated on the
INT pin when a good quality channel is found in the CCA
mode.
5.12 RDS/RBDS
a. According to the formula on Section 5.10, derive
channel index of the desired channel.
b. Write channel index to Reg07h and Reg0Ah[1:0].
c. Set CHCS (Reg00h[1]) bit low to disable the CCA
function and select manual operation.
d. Set the CCA_CH_DIS (Reg00h[0]) bit high to select
manual tuning channel.
In receive mode, setting RDSEN (Reg00h[3]) bit high
will enable the RDS function. Once the device receives an
RDS signal, the RDSSYNC (Reg13h[4]) will be high. On
reception of a RDS signal, if RDS_RXTXTUPD
(Reg13h[7]) bit is toggled, or the INT pin will output a
4.55ms low pulse when hardware interrupt function is
e. Set RXREQ (Reg00[4]) bit high and STNBY
(Reg00h[5] bit low to enter receive mode.
3) Auto Seek (CCA)
Rev 0.08 (02/10)
Copyright ©2010 by Quintic Corporation
Page 16
Confidential A
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice.
Free Datasheet http://www.datasheet4u.com/










页数 39 页
下载[ QN8035.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
QN8035Single-Chip Low-Power FM ReceiverQuintic
Quintic
QN8036High Performance Digital FM TransceiverQuintic
Quintic

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap