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PDF ( 数据手册 , 数据表 ) UJA1164

零件编号 UJA1164
描述 Mini high-speed CAN system basis chip
制造商 NXP Semiconductors
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UJA1164 数据手册, 描述, 功能
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
Rev. 2 — 17 April 2014
Product data sheet
1. General description
The UJA1164 is a mini high-speed CAN System Basis Chip (SBC) containing an
ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a
microcontroller. It also features a watchdog and a Serial Peripheral Interface (SPI). The
UJA1164 can be operated in a very low-current Standby mode with bus wake-up
capability and supports ISO 11898-6 compliant autonomous CAN biasing.
The UJA1164 implements the standard CAN physical layer as defined in the current
ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898
including CAN FD, additional timing parameters defining loop delay symmetry are
included. This implementation enables reliable communication in the CAN FD fast phase
at data rates up to 2 Mbit/s.
A number of configuration settings are stored in non-volatile memory, allowing the SBC to
be adapted for use in a specific application. This makes it possible to configure the
power-on behavior of the UJA1164 to meet the requirements of different applications.
2. Features and benefits
2.1 General
ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller
supply (V1)
Bus connections are truly floating when power to pin BAT is off
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6 kV ESD protection, according to IEC 61000-4-2 on the CAN bus pins and on pin
BAT
CAN bus pins short-circuit proof to 58 V
Battery and CAN bus pins protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Standby mode with full wake-up capability







UJA1164 pdf, 数据表
NXP Semiconductors
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
Even in Forced Normal mode, a reset event (e.g. an external reset or a V1 undervoltage)
will trigger a transition to Reset mode with normal Reset mode behavior (except that the
transmitter remains active if there is no V1 undervoltage). However, when the UJA1164
exits Reset mode, it will return to Forced Normal mode instead of switching to Standby
mode.
In Forced Normal mode, only the Main status register, the Watchdog status register, the
Identification register and registers stored in non-volatile memory can be read. The
non-volatile memory area is fully accessible for writing as long as the UJA1164 is in the
factory preset state (for details see Section 6.9).
The UJA1164 switches from Reset mode to Forced Normal mode if bit FNMC = 1.
6.1.1.7 Hardware characterization for the UJA1164 operating modes
Table 3. Hardware characterization by functional block
Block
Operating mode
Off Forced Normal Standby
V1
off[1]
on
on
RSTN
LOW HIGH
HIGH
SPI disabled active
active
Watchdog off
off
determined by bits
WMC (see Table 7)[2]
CAN off Active
Offline
RXD
V1 level CAN bit stream V1 level/LOW if
wake-up detected
Normal
Reset
on on
HIGH
LOW
active
disabled
determined by bits WMC[2] off
Overtemp
off
LOW
disabled
off
Active/ Offline/ Listen-only Offline
(determined by bits CMC;
see Table 14)
off
CAN bit stream if
CMC = 01/10/11;
otherwise same as
Standby
V1 level/LOW V1 level/LOW
if wake-up if wake-up
detected
detected
[1] When the SBC switches from Reset, Standby or Normal mode to Off mode, V1 behaves as a current source during power down while
VBAT is between 3 V and 2 V.
[2] Window mode is only active in Normal mode.
6.1.2 System control registers
The operating mode is selected via bits MC in the Mode control register. The Mode control
register is accessed via SPI address 0x01 (see Section 6.13).
Table 4. Mode control register (address 01h)
Bit Symbol
Access Value
Description
7:3 reserved R
-
2:0 MC
R/W
mode control:
100 Standby mode
111 Normal mode
The Main status register can be accessed to monitor the status of the overtemperature
warning flag and to determine whether the UJA1164 has entered Normal mode after initial
power-up. It also indicates the source of the most recent reset event.
UJA1164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 53







UJA1164 equivalent, schematic
NXP Semiconductors
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
transmitter is supplied from V1. The UJA1164 includes additional timing parameters on
loop delay symmetry to ensure reliable communication in fast phase at data rates up to
2 Mbit/s, as used in CAN FD networks.
The CAN transceiver supports autonomous CAN biasing as defined in ISO 11898-6,
which helps to minimize RF emissions. CANH and CANL are always biased to 2.5 V when
the transceiver is in Active or Listen-only modes (CMC = 01/10/11).
Autonomous biasing is active in CAN Offline mode - to 2.5 V if there is activity on the bus
(CAN Offline Bias mode) and to GND if there is no activity on the bus for t > tto(silence)
(CAN Offline mode).
This is useful when the node is disabled due to a malfunction in the microcontroller. The
SBC ensures that the CAN bus is correctly biased to avoid disturbing ongoing
communication between other nodes. The autonomous CAN bias voltage is derived
directly from VBAT.
6.6.1 CAN operating modes
The integrated CAN transceiver supports four operating modes: Active, Listen-only,
Offline and Offline Bias (see Figure 5). The CAN transceiver operating mode depends on
the UJA1164 operating mode and on the setting of bits CMC in the CAN control register
(Table 14).
When the UJA1164 is in Normal mode, the CAN transceiver operating mode (Active,
Listen-only or Offline) can be selected via bits CMC in the CAN control register (Table 14).
When the UJA1164 is in Standby mode, the transceiver is forced to Offline or Offline Bias
mode (depending on bus activity).
6.6.1.1 CAN Active mode
In CAN Active mode, the transceiver can transmit and receive data via CANH and CANL.
The differential receiver converts the analog data on the bus lines into digital data, which
is output on pin RXD. The transmitter converts digital data generated by the CAN
controller (input on pin TXD) into analog signals suitable for transmission over the CANH
and CANL bus lines.
CAN Active mode is selected when CMC = 01 or 10. When CMC = 01, V1/CAN
undervoltage detection is enabled and the transceiver will go to CAN Offline or CAN
Offline Bias mode when the voltage on V1 drops below the 90 % threshold. When
CMC = 10, V1/CAN undervoltage detection is disabled. The transmitter will remain active
until the voltage on V1 drops below the V1 reset threshold (selected via bits V1RTC). The
SBC will then switch to Reset mode and the transceiver will switch to CAN Offline or CAN
Offline Bias mode.
The CAN transceiver is in Active mode when:
the UJA1164 is in Normal mode (MC = 111) and the CAN transceiver has been
enabled by setting bits CMC in the CAN control register to 01 or 10 (see Table 14)
and:
if CMC = 01, the voltage on pin V1 is above the 90 % undervoltage threshold
if CMC = 10, the voltage on pin V1 is above the V1 reset threshold
UJA1164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 53










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