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PDF ( 数据手册 , 数据表 ) ADF4151

零件编号 ADF4151
描述 Fractional-N/Integer-N PLL Synthesizer
制造商 Analog Devices
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ADF4151 数据手册, 描述, 功能
Data Sheet
Fractional-N/Integer-N PLL Synthesizer
ADF4151
FEATURES
GENERAL DESCRIPTION
Fractional-N synthesizer and integer-N synthesizer
RF bandwidth to 3.5 GHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Separate charge pump supply (VP) allows extended tuning
voltage (up to 5.5 V) in 3 V systems
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable RF output phase
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast lock mode
Cycle slip reduction
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,
PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
The ADF4151 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
if used with an external voltage controlled oscillator (VCO),
loop filter, and external reference frequency.
The ADF4151 is used with external VCO parts and is footprint
and software compatible with the ADF4350. The part consists
of a low noise digital phase frequency detector (PFD), a precision
charge pump, and a programmable reference divider. There is
a Σ-Δ based fractional interpolator to allow programmable
fractional-N division. The INT, FRAC, and MOD registers
define an overall N divider [N = (INT + (FRAC/MOD))]. The
RF output phase is programmable for applications that require
a particular phase relationship between the output and the
reference. The ADF4151 also features cycle slip reduction
circuitry, leading to faster lock times without the need for
modifications to the loop filter.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V that can be powered down when not in use.
The ADF4151 is available in a 5 mm × 5 mm package.
FUNCTIONAL BLOCK DIAGRAM
SDVDD
AVDDx
DVDD
VP
RSET
REFIN
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
FLO SWITCH
MUXOUT
SW
LD
CPOUT
INTEGER FRACTION MODULUS
REG
REG
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
RFIN+
RFIN
N COUNTER
ADF4151
CE AGND
Figure 1.
CPGND
SDGND
DGND
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
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ADF4151 pdf, 数据表
ADF4151
Data Sheet
Pin No.
22
25
26, 27
28
29
30
31
32
Mnemonic
RSET
LD
DGND
DVDD
REFIN
MUXOUT
SDGND
SDVDD
EP
Description
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage
bias at the RSET pin is 0.49 V. The relationship between ICP and RSET is
I CP
=
22.95
RSET
where:
RSET = 5.1 kΩ.
ICP = 4.5 mA.
Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock; a logic low output indicates loss of PLL
lock.
Digital Ground. Ground return path for DVDD.
Digital Power Supply. This pin should be the same voltage as AVDD. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator.
Power Supply Pin for the Digital Σ-Δ Modulator. Should be the same voltage as AVDDx. Decoupling capacitors
to the ground plane are to be placed as close as possible to this pin.
The exposed pad must be connected to GND.
Rev. B | Page 8 of 28
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ADF4151 equivalent, schematic
ADF4151
Data Sheet
RESERVED
CLK
DIV
MODE
12-BIT CLOCK DIVIDER VALUE
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 F3 F2 0 0 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(1)
F1
CYCLE SLIP
REDUCTION
0 DISABLED
1 ENABLED
C2 C1 CLOCK DIVIDER MODE
0 0 CLOCK DIVIDER OFF
0 1 FAST LOCK ENABLE
1 0 RESYNC ENABLE
1 1 RESERVED
F2
CHARGE
CANCELLATION
0 DISABLED
1 ENABLED
D12 D11 .......... D2
0 0 .......... 0
0 0 .......... 0
0 0 .......... 1
0 0 .......... 1
. . .......... .
. . .......... .
. . .......... .
1 1 .......... 0
1 1 .......... 0
1 1 .......... 1
1 1 .......... 1
D1
0
1
0
1
.
.
.
0
1
0
1
CLOCK DIVIDER VALUE
0
1
2
3
.
.
.
4092
4093
4094
4095
F3
ANTIBACKLASH
PULSE WIDTH
0 6ns (FRAC-N)
1 3ns (INT_N)
Figure 22. Register 3 (R3)
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(0) C1(0)
Figure 23. Register 4 (R4)
RESERVED
LD PIN
MODE
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 D15 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(0) C1(1)
D1 5
0
0
1
1
D1 4
0
1
0
1
LOCK DETECT PIN OPERATION
LOW
DIGITAL LOCK DETECT
LOW
HIGH
Figure 24. Register 5 (R5)
Rev. B | Page 16 of 28
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