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PDF ( 数据手册 , 数据表 ) LG122321-SFLYH6V

零件编号 LG122321-SFLYH6V
描述 LCD Module
制造商 ETC
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LG122321-SFLYH6V 数据手册, 描述, 功能
LCD Module Specification
Model: LG122321-SFLYH6V
Table of Contents
COVER & CONTENTS ······················· 1
BASIC SPECIFICATIONS ····················· 2
ABSOLUTE MAXIMUM RATINGS ················· 3
ELECTRICAL CHARACTERISTICS ··············· 4
MPU INTERFACE ························· 7
OPERATING PRINCIPLES & METHODES ··········· 9
INSTRUCTION CODES ······················ 11
POWER ON INITIALIZATION ··················· 16
DISPLAY DATA RAM ADDRESS MAP ············· 17
CONNECTION WITH 8051 FAMILY MPU ············ 18
ELECTROOPTICAL CHARACTERISTICS ·········· 19
DIMENSIONAL OUTLINE ····················· 11
LCD MODULE NUMBERING SYSTEM ············· 22
PRECAUTIONS FOR USE OF LCD MODULE ········· 23
Free Datasheet http:







LG122321-SFLYH6V pdf, 数据表
LG122321-SFLYH6V
-8-
Level of /RST
Lactive
Hactive
Type of MPU
68 MPU
80 MPU
A0
E
R/W
/CS DB0~DB7
↑↑↑
/RD /WR
For 68 series MPU: /RST active L, reset at rising edge, /RST=Hafter reset.
For 80 series MPU: /RST active H, reset at falling edge, /RST=Lafter reset.
4.2 Identification of data bus signal
The SED1520 uses a combination of A0, E, R/W (/RD, /WR) to identify the data bus
signal.
Common
A0
1
1
0
0
68 MPU
R/W
1
0
1
0
80 MPU
/RD /WR
01
10
01
10
Function
Read display data
Write display data
Read status
Write instruction
When interface with 68 series MPU:
For read operation (/CS=0, R/W=1), display data or status appears at DB0 to DB7 while E
is in Hlevel; for write operation (/CS=0, R/W=0), display data or instruction code at DB0
to DB7 is latched to SED1520 at the falling edge of E.
When interface with 80 series MPU:
For read operation (/CS=0, /WR=1), display data or status appears at DB0 to DB7 while
/RD is in Llevel; for write operation (/CS=0, /RD=1), display data or instruction code at
DB0 to DB7 is latched to SED1520 at the rising edge of /WR.
4.3 Access to Display Data RAM and Internal Register
The SED1520 is operating as one of pipe-line processor by the bus-holder connecting to
the internal data bus to adjust the operation frequency between MPU and the display data
RAM or internal register.
When MPU writes data into the display data RAM, the data is held in the bus-holder at
first, and then written into the display data RAM automatically by internal operation.
In the case when MPU reads the content of the display data RAM, in the first data read
cycle (dummy), the data is stored on the bus-holder. In the next data read cycle, the data
is read from the bus-holder to the system bus. Therefore, one dummy read is required
after address setting or write cycle.
Free Datasheet http://www.datasheet4u.com/







LG122321-SFLYH6V equivalent, schematic
LG122321-SFLYH6V
- 16 -
(b) Stop the oscillation or inhibit the external clock input.
(c) Keep the display data and operating mode.
The power save mode is released by display on or static drive off instruction.
A resistor division circuit is used to give LCD driving voltage level. To reduce the total
current consumption, the current flowing into the resistors must be cut off by the power
save signal.
7. POWER ON INITIALIZATION
When power on, take the following sequence to initialize the LCD module.
Power on
/RST:
interface with 68 MPU
OR
/RST:
interface with 80 MPU
Display On/Off : Off
Display Start Line : 0
Static Drive On/Off : Off
Column Address Set : 0
Page Address Set : 0
Duty Select : 1/32
ADC Select : Forward
Read Modify Write : Off (End)
End of initialization
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