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PDF ( 数据手册 , 数据表 ) ADRF6806

零件编号 ADRF6806
描述 50 MHz to 525 MHz Quadrature Demodulator
制造商 Analog Devices
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ADRF6806 数据手册, 描述, 功能
Data Sheet
50 MHz to 525 MHz Quadrature
Demodulator with Fractional-N PLL and VCO
ADRF6806
FEATURES
GENERAL DESCRIPTION
IQ demodulator with integrated fractional-N PLL
LO frequency range: 50 MHz to 525 MHz
For the following specifications (LPEN = 0)/(LPEN = 1):
Input P1dB: 12.2 dBm/10.6 dBm
Input IP3: 28.5 dBm/25.2 dBm
Noise figure (DSB): 12.2/11.4
Voltage conversion gain: 1 dB/4.2 dB
Quadrature demodulation accuracy
Phase accuracy: <0.5°
Amplitude accuracy: <0.1 dB
Baseband demodulation: 135 MHz, 3 dB bandwidth
SPI serial interface for PLL programming
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
QAM/QPSK RF/IF demodulators
Cellular W-CDMA/CDMA/CDMA2000
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX
The ADRF6806 is a high dynamic range IQ demodulator with
integrated PLL and VCO. The fractional-N PLL/synthesizer
generates a frequency in the range of 2.8 GHz to 4.2 GHz. A
programmable quadrature divider (divide ratio = 4 to 80) divides
the output frequency of the VCO down to the required local
oscillator (LO) frequency to drive the mixers in quadrature.
Additionally, an output divider (divide ratio = 4 to 8) generates
a divided-down VCO signal for external use.
The PLL reference input is supported from 10 MHz to 160 MHz.
The phase detector output controls a charge pump whose output
is integrated in an off-chip loop filter. The loop filter output is
then applied to an integrated VCO.
The IQ demodulator mixes the differential RF input with the
complex LO derived from the quadrature divider. The differential
I and Q output paths have excellent quadrature accuracy and
can handle baseband signaling or complex IF up to 120 MHz.
A reduced power mode of operation is also provided by
programming the serial interface registers to reduce current
consumption, with slightly degraded input linearity and output
current drive.
The ADRF6806 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, exposed-paddle,
RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is
specified over the −40°C to +85°C temperature range.
LON 37
LOP 38
GND 11
DATA 12
CLK 13
LE 14
GND 15
REFIN 6
GND 7
MUXOUT 8
GND VCCLO VCCLO
35 34
17
FUNCTIONAL BLOCK DIAGRAM
LOSEL
36
BUFFER
CTRL
BUFFER
DIV
÷4,
÷6,
÷8
IBBP
33
ADRF6806
IBBN GND
32 31
30 GND
29 DECL3
28 VCCRF
27 GND
SPI
INTERFACE
×2
MUX
÷2
÷4
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
BUFFER
PRESCALER
÷2
MUX
DIVIDER
÷2
TO
÷40
VCO
CORE
TEMP
SENSOR
+
PHASE
FREQUENCY
DETECTOR
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
2.5V LDO
VCO LDO
QUAD
÷2
26 RFIN
25 RFIP
24 GND
23 VOCM
22 VCCBB
21 GND
1
VCC1
2
VCC1
34
5
9 10 39 40
16
CPOUT GND RSET DECL2 VCC2 VTUNE DECL1 GND
18 19 20
QBBP QBBN GND
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
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ADRF6806 pdf, 数据表
ADRF6806
Data Sheet
Pin No.
8
9
10
12
13
14
17, 34
18, 19
22
23
25, 26
28
29
32, 33
36
37, 38
39
40
Mnemonic
MUXOUT
DECL2
VCC2
DATA
CLK
LE
VCCLO
QBBP, QBBN
VCCBB
VOCM
RFIP, RFIN
VCCRF
DECL3
IBBN, IBBP
LOSEL
LON, LOP
VTUNE
DECL1
EP
Description
Multiplexer Output. This output can be programmed to provide the reference output signal or the
lock detect signal. The output is selected by programming the appropriate register.
Connect a 0.1 μF capacitor between this pin and ground.
The 3.3 V power supply for the 2.5 V LDO.
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into
one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word.
The 3.3 V power supply for the LO path blocks.
Demodulator Q-Channel Differential Baseband Outputs (Differential Output Impedance of 28 Ω).
The 5 V power supply for the demodulator blocks.
Baseband Common-Mode Reference Input; 1.65 V nominal. It sets the dc common-mode level of
the IBBx and QBBx outputs.
Differential 100 Ω, Internally Biased RF Inputs. These pins must be ac-coupled.
The 5 V power supply for the demodulator blocks.
Connect a 2.2 μF capacitor between this pin and ground.
Demodulator I-Channel Differential Baseband Outputs (Differential Output Impedance of 28 Ω).
LO Select. Connect this pin to ground for the simplest operation and to completely control the LO
path and input/output direction from the register SPI programming.
For additional control without register reprogramming, this input pin can determine whether the
LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is set
low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The externally
applied LO drive must be at M×LO frequency (where M corresponds to the main LO divider setting). LON
and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set high and
the LXL bit of Register 5 (DB4) low. The output frequency is controlled by the LO output divider bits
in Register 7. This pin should not be left floating.
Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency
divided version of the internal VCO is available on these pins. When the internal LO generation is
disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds to
the main divider setting). (Differential Input/Output Impedance of 50 Ω)
VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input
voltage range on this pin is 1.0 V to 2.8 V.
Connect a 10 μF capacitor between this pin and ground as close to the device as possible because
this pin serves as the VCO supply and loop filter reference.
Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Rev. B | Page 8 of 36
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ADRF6806 equivalent, schematic
ADRF6806
Data Sheet
Register 1—Modulus Divide Control
With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 34. The MOD value is the preset
fractional modulus ranging from 1 to 2047.
DB23 DB22
00
DB21
0
DB20
0
DB19
0
DB18 DB17 DB16 DB15
0000
DB14
0
DB13
MD10
MODULUS DIVIDE RATIO
DB12 DB11 DB10 DB9 DB8 DB7 DB6
MD9 MD8 MD7 MD6 MD5 MD4 MD3
DB5
MD2
DB4
MD1
DB3
MD0
CONTROL BITS
DB2 DB1 DB0
C3(0) C2(0) C1(1)
MD10
0
0
...
...
1
...
...
1
MD9
0
0
...
...
1
...
...
1
MD8
0
0
...
...
0
...
...
1
MD7
0
0
...
...
0
...
...
1
MD6
0
0
...
...
0
...
...
1
MD5
0
0
...
...
0
...
...
1
MD4
0
0
...
...
0
...
...
1
MD3
0
0
...
...
0
...
...
1
MD2
0
0
...
...
0
...
...
1
MD1
0
1
...
...
0
...
...
1
MD0
1
0
...
...
0
...
...
1
MODULUS VALUE
1
2
...
...
1536 (DEFAULT)
...
...
2047
Register 2—Fractional Divide Control
Figure 34. Modulus Divide Control Register (R1)
With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 35. The FRAC value is the preset
fractional modulus ranging from 0 to MOD − 1.
DB23
0
DB22
0
DB21 DB20 DB19 DB18
0000
DB17 DB16
00
DB15
0
DB14
0
DB13
FD10
DB12
FD9
FRACTIONAL DIVIDE RATIO
DB11 DB10 DB9 DB8 DB7 DB6
FD8 FD7 FD6 FD5 FD4 FD3
DB5
FD2
DB4
FD1
DB3
FD0
CONTROL BITS
DB2 DB1 DB0
C3(0) C2(1) C1(0)
FD10
0
0
...
...
0
...
...
FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1
000000000
000000000
... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ...
110000000
... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ...
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
Figure 35. Fractional Divide Control Register (R2)
FD0
0
1
...
...
0
...
...
FRACTIONAL VALUE
0
1
...
...
768 (DEFAULT)
...
...
<MDR
Register 3—Σ-Δ Modulator Dither Control
With R3[2:0] set to 011, the on-chip Σ-Δ modulator dither control register is programmed as shown in Figure 36. The dither restart value
can be programmed from 0 to 217 to 1, though a value of 1 is typically recommended.
DB23
0
DITHER
MAGNITUDE
DB22 DB21
DITH1 DITH0
DITHER
ENABLE
DITHER RESTART VALUE
CONTROL BITS
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)
DEN
0
1
DITHER ENABLE
DISABLE
ENABLE (DEFAULT, RECOMMENDED)
DITH1
0
0
1
1
DITH0
0
1
0
1
DITHER MAGNITUDE
15 (DEFAULT)
7
3
1 (RECOMMENDED)
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
00000000000000001
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
11111111111111111
DITHER RESTART
VALUE
0x00001 (DEFAULT)
...
...
0x1FFFF
Figure 36. Σ-Δ Modulator Dither Control Register (R3)
Rev. B | Page 16 of 36
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