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PDF ( 数据手册 , 数据表 ) AD9119

零件编号 AD9119
描述 (AD9119 / AD9129) RF Digital-to-Analog Converter
制造商 Analog Devices
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AD9119 数据手册, 描述, 功能
Data Sheet
FEATURES
DAC update rate: up to 5.6 GSPS
Direct RF synthesis at 2.8 GSPS data rate
DC to 1.4 GHz in baseband mode
DC to 1.0 GHz in 2× interpolation mode
1.4 GHz to 4.2 GHz in Mix-Mode
Bypassable 2× interpolation
Excellent dynamic performance
Supports DOCSIS 3.0 wideband ACLR/harmonic performance
8 QAM carriers: ACLR > 65 dBc
Industry-leading single/multicarrier IF or RF synthesis
4-carrier W-CDMA ACLR at 2457.6 MSPS
fOUT = 900 MHz, ACLR = 71 dBc (baseband mode)
fOUT = 2100 MHz, ACLR = 68 dBc (Mix-Mode)
fOUT = 2700 MHz, ACLR = 67 dBc (Mix-Mode)
Dual-port LVDS and DHSTL data interface
Up to 1.4 GSPS operation
Source synchronous DDR clocking with parity bit
Low power: 1.0 W at 2.8 GSPS (1.3 W at 5.6 GSPS)
APPLICATIONS
Broadband communications systems
CMTS/VOD
Wireless infrastructure: W-CDMA, LTE, point-to-point
Instrumentation, automatic test equipment (ATE)
Radars, jammers
GENERAL DESCRIPTION
The AD9119/AD9129 are high performance, 11-/14-bit RF digital-
to-analog converters (DACs) supporting data rates up to 2.8 GSPS.
The DAC core is based on a quad-switch architecture that enables
dual-edge clocking operation, effectively increasing the DAC
update rate to 5.6 GSPS when configured for Mix-Mode™ or 2×
interpolation. The high dynamic range and bandwidth enable
multicarrier generation up to 4.2 GHz.
In baseband mode, wide bandwidth capability combines with high
dynamic range to support from 1 to 158 contiguous carriers for
CATV infrastructure applications. A choice of two optional 2×
interpolation filters is available to simplify the postreconstruction
filter by effectively increasing the DAC update rate by a factor of 2.
In Mix-Mode operation, the AD9119/AD9129 can reconstruct
RF carriers in the second and third Nyquist zone while still
maintaining exceptional dynamic range up to 4.2 GHz. The
high performance NMOS DAC core features a quad-switch
architecture that enables industry-leading direct RF synthesis
performance with minimal loss in output power. The output
current can be programmed over a range of 9.5 mA to 34.4 mA.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
11-/14-Bit, 5.6 GSPS,
RF Digital-to-Analog Converter
AD9119/AD9129
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
I250U VREF
SDIO
SDO
CS
SCLK
FRM_x
(FRAME/
PARITY)
P0_D[13:0]P,
P0_D[13:0]N
DCI_x
SPI
DLL
AD9129
1.2V
MIX-
NORMAL MODE
BASEBAND
MODE
Tx DAC
CORE
IOUTP
IOUTN
P1_D[13:0]P,
P1_D[13:0]N
PLL
DCO_x
CLOCK
DISTRIBUTION
Figure 1.
DCR
DACCLK_x
The AD9119/AD9129 include several features that may further
simplify system integration. A dual-port, source synchronous
LVDS interface simplifies the data interface to a host FPGA/ASIC.
A differential frame/parity bit is also included to monitor the
integrity of the interface. On-chip delay locked loops (DLLs)
are used to optimize timing between different clock domains.
A serial peripheral interface (SPI) is used to configure the
AD9119/AD9129 and monitor the status of readback registers.
The AD9119/AD9129 is manufactured on a 0.18 µm CMOS
process and operates from +1.8 V and −1.5 V supplies. It is
supplied in a 160-ball chip scale package ball grid array.
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
support RF signal synthesis of up to 4.2 GHz.
2. Dual-port interface with double data rate (DDR) LVDS
data receivers supports 2800 MSPS maximum conversion rate.
3. Manufactured on a CMOS process; a proprietary switching
technique enhances dynamic performance.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/







AD9119 pdf, 数据表
AD9119/AD9129
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
I250U
VREF
VSSA
VSSA
VDDA SH
IOUTP
IOUTN VDDA SH
VDDA
VDDA
VDDA
VSSC
VSSC
VSSC
B
VDDA
VDDA
VSSA
VSSA
VSSA
VDDA SH VDDA SH
VDDA
VDDA
VDDA
VDDA
VSSC
VSSC
SYNC
C
DACCLK_N
VDDA
VDDA
VSSA
VSSA
VSSA
VDDA
VDDA
VDDA
VDDA
VSSC
VSSC
VSS
VSS
D
DACCLK_P
VDDA
VDDA
VDDA
VSSC
VSSC
VDDA
VSSC
VSSC
VSSC
VSSC
VSS
VSS
VSS
E
VDDA
VDDA
VSSC
VSSC
VSS VSS VSS VSS
F
VSSC
VSSC
VSSC
VSSC
VSS VSS VSS VSS
G VSS VSS VSS VSSC
H
RESET
IRQ
VSS
VSS
AD9119
VSS VDD VDD VDD
VDD
VDD
VDD
VDD
J
SDIO
SDO
VDD
VDD
VDD
VDD
VDD
VDD
K
SCLK
CS
DCI_P
DCI_N
DCO_P
DCO_N
FRM_P
FRM_N
L
NC
NC
NC
P1_D0P
P1_D1P
P1_D2P
P1_D3P
P1_D4P
P1_D5P
P1_D6P
P1_D7P
P1_D8P
P1_D9P P1_D10P
M
NC
NC
NC
P1_D0N
P1_D1N
P1_D2N
P1_D3N
P1_D4N
P1_D5N
P1_D6N
P1_D7N
P1_D8N
P1_D9N P1_D10N
N
NC
NC
NC
P0_D0P
P0_D1P
P0_D2P
P0_D3P
P0_D4P
P0_D5P
P0_D6P
P0_D7P
P0_D8P
P0_D9P P0_D10P
P
NC
NC
NC
P0_D0N
P0_D1N
P0_D2N
P0_D3N
P0_D4N
P0_D5N
P0_D6N
P0_D7N
P0_D8N
P0_D9N P0_D10N
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Table 8. AD9119 Pin Function Descriptions
Pin No.
Mnemonic
A1 I250U
A2
A3, A4, B3, B4, B5, C4, C5, C6
A5, A8, B6, B7
A9, A10, A11, B1, B2, B8, B9, B10,
B11, C2, C3, C7, C8, C9, C10, D2,
D3, D4, D7, E1, E2
VREF
VSSA
VDDA SH
VDDA
Figure 2. AD9119 Pin Configuration
Description
Nominal 1.0 V Reference. Tie this pin to VSSA via a 4.0 kΩ resistor to generate
a 250 µA reference current.
Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor.
−1.5 V Analog Supply Voltage Input.
+1.8 V Analog Supply Shield. Tie these pins to VDDA at the DAC.
+1.8 V Analog Supply Voltage Input.
Rev. 0 | Page 8 of 68
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AD9119 equivalent, schematic
AD9119/AD9129
Data Sheet
AC (Mix-Mode)
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
REF 0dBm
0
REF 5dBm
5
–10 –5
–20 –15
–30 –25
–40 –35
–50 –45
–60 –55
–70 –65
–80 –75
–90 –85
–100
START 20MHz
RES BW 20kHz
VBW 20kHz
STOP 2.6GHz
SWEEP 7.78s (1001 pts)
Figure 24. Single Tone Spectrum at fOUT = 2350 MHz
–95
START 20MHz
RES BW 20kHz
VBW 20kHz
STOP 2.6GHz
SWEEP 7.78s (1001 pts)
Figure 27. Single-Tone Spectrum at fOUT = 1600 MHz
–40
1600MSPS
2200MSPS
2800MSPS
–50
–60
–70
–80
–90
500
1000
1500
2000
fOUT (MHz)
2500
Figure 25. SFDR vs. fOUT over fDAC
3000
–50
–55
–60
–65
–70
–75
–80
–85
500
1600MSPS
2200MSPS
2800MSPS
1000
1500
2000
2500
fOUT (MHz)
Figure 28. IMD vs. fOUT over fDAC
3000
–145
–145
–150
–150
–155
–155
–160
–160
–165
–165
–170
1000
1500 2000 2500 3500 3500 4000
fOUT (MHz)
Figure 26. Single-Tone NSD vs. fOUT
4500
–170
1500
2000
2500
3000
3500
fOUT (MHz)
Figure 29. W-CDMA NSD vs. fOUT
4000
Rev. 0 | Page 16 of 68
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