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PDF ( 数据手册 , 数据表 ) NOIV1SN5000A

零件编号 NOIV1SN5000A
描述 VITA 5000 5.3 Megapixel 75 FPS Global Shutter CMOS Image Sensor
制造商 ON Semiconductor
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NOIV1SN5000A 数据手册, 描述, 功能
NOIV1SN5000A
VITA 5000 5.3 Megapixel
75 FPS Global Shutter
CMOS Image Sensor
Features
QSXGA: 2592 x 2048 Active Pixels
4.8 mm x 4.8 mm Pixel Size
1 inch Optical Format
Monochrome (SN) or Color (SE)
75 Frames per Second (fps) at Full Resolution (LVDS)
On-chip 10-bit Analog-to-Digital Converter (ADC)
8-bit or 10-bit Output Mode
Eight LVDS Serial Outputs
Random Programmable Region of Interest (ROI) Readout
Pipelined and Triggered Global Shutter, Rolling Shutter
On-chip Fixed Pattern Noise (FPN) Correction
Serial Peripheral Interface (SPI)
Automatic Exposure Control (AEC)
Phase Locked Loop (PLL)
High Dynamic Range (HDR)
Dual Power Supply (3.3 V and 1.8 V)
0°C to 70°C Operational Temperature Range
68-pin LCC
1000 mW Power Dissipation in 10-bit Mode
These Devices are PbFree and are RoHS Compliant
http://onsemi.com
Figure 1. VITA 5000 Photo
Applications
Machine Vision
Motion Monitoring
Security
Barcode Scanning (2D)
Description
The VITA 5000 is a 1 inch Quad Super eXtended Graphics Array (QSXGA) CMOS image sensor with a pixel array of 2592
by 2048.
The high sensitivity 4.8 mm x 4.8 mm pixels support pipelined and triggered global shutter readout modes and can also be
operated in a low noise rolling shutter mode. In rolling shutter mode, the sensor supports correlated double sampling readout,
reducing noise and increasing the dynamic range.
The sensor has on-chip programmable gain amplifiers and 10-bit A/D converters. The integration time and gain parameters
can be reconfigured without any visible image artifact. Optionally the on-chip automatic exposure control loop (AEC) controls
these parameters dynamically. The image’s black level is either calibrated automatically or can be adjusted by adding a user
programmable offset.
A high level of programmability using a four wire serial peripheral interface enables the user to read out specific regions
of interest. Up to 8 regions can be programmed, achieving even higher frame rates.
The image data interface consists of eight LVDS lanes, facilitating frame rates up to 75 frames per second. Each channel runs
at 620 Mbps. A separate synchronization channel containing payload information is provided to facilitate the image
reconstruction at the receiver end.
The VITA 5000 is packaged in a 68-pin LCC package and is available in a monochrome and color version.
Contact your local ON Semiconductor office for more information.
© Semiconductor Components Industries, LLC, 2013
June, 2013 Rev. 6
1
Publication Order Number:
NOIV1SN5000A/D
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NOIV1SN5000A pdf, 数据表
NOIV1SN5000A
Image Core
The image core consists of:
Pixel Array
Address Decoders and Row Drivers
Pixel Biasing
The pixel array contains 2592 (H) x 2048 (V) readable
pixels with a pixel pitch of 4.8 mm. Four dummy pixel rows
and columns are placed at every side of the pixel array to
eliminate possible edge effects. The sensor uses a 5T pixel
architecture, which makes it possible to read out the pixel
array in global shutter mode with double sampling (DS), or
in rolling shutter mode with correlated double sampling
(CDS).
The function of the row drivers is to access the image array
line by line, or all lines together, to reset or read the pixel
data. The row drivers are controlled by the on-chip
sequencer and can access the pixel array in global and rolling
shutter modes.
The pixel biasing block guarantees that the data on a pixel
is transferred properly to the column multiplexer when the
row drivers select a pixel line for readout.
Phase Locked Loop
The PLL accepts a (low speed) clock and generates the
required high speed clock. Optionally this PLL can be
bypassed. Typical input clock frequency is 62 MHz.
LVDS Clock Receiver
The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Typical input clock frequency is 310 MHz in 10-bit mode
and 248 MHz in 8-bit mode. The clock input needs to be
terminated with a 100 W resistor.
Column Multiplexer
All pixels of one image row are stored in the column
sample-and-hold (S/H) stages. These stages store both the
reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 8 parallel differential outputs operating at a
frequency of 31 MHz.
At this stage, the reset signal and integrated signal values
are transferred into an FPN-corrected differential signal.
The column multiplexer also supports read-1-skip-1 and
read-2-skip-2 mode. Enabling this mode can speed up the
frame rate, with a decrease in resolution.
Bias Generator
The bias generator generates all required reference
voltages and bias currents that the on-chip blocks use. An
external resistor of 47 kW, connected between pin
IBIAS_MASTER and gnd_33, is required for the bias
generator to operate properly.
Analog Front End
The AFE contains 8 channels, each containing a PGA and
a 10-bit ADC.
For each of the 8 channels, a pipelined 10-bit ADC is used
to convert the analog image data into a digital signal, which
is delivered to the data formatting block. A black calibration
loop is implemented to ensure that the black level is mapped
to match the correct ADC input level.
Data Formatting
The data block receives data from two ADCs and
multiplexes this data to one data stream. A cyclic
redundancy check (CRC) code is calculated on the passing
data.
A frame synchronization data block transmits
synchronization codes such as frame start, line start, frame
end, and line end indications.
The data block calculates a CRC once per line for every
channel. This CRC code can be used for error detection at the
receiving end.
Serializer and LVDS Interface
The serializer and LVDS interface block receives the
formatted (10-bit or 8-bit) data from the data formatting
block. This data is serialized and transmitted by the LVDS
output driver.
In 10-bit mode, the maximum output data rate is 620 Mbps
per channel. In 8-bit mode, the maximum output data rate is
496 Mbps per channel.
In addition to the LVDS data outputs, two extra LVDS
outputs are available. One of these outputs carries the output
clock, which is skew aligned to the output data channels. The
second LVDS output contains frame format synchronization
codes to serve system-level image reconstruction.
Sequencer
The sequencer:
Controls the image core. Starts and stops integration in
rolling and global shutter modes and control pixel
readout.
Operates the sensor in master or slave mode.
Applies the window settings. Organizes readouts so that
only the configured windows are read.
Controls the column multiplexer and analog core.
Applies gain settings and subsampling modes at the
correct time, without corrupting image data.
Starts up the sensor correctly when leaving standby
mode.
Automatic Exposure Control
The AEC block implements a control system to modulate
the exposure of an image. Both integration time and gains
are controlled by this block to target a predefined
illumination level.
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NOIV1SN5000A equivalent, schematic
NOIV1SN5000A
Required Register Upload
In this phase, the ‘reserved’ register settings are uploaded
through the SPI register. Different settings are not allowed
and may cause the sensor to malfunction. The required
uploads are listed in Table 8.
NOTE: This table is subject to change.
Table 8. REQUIRED REGISTER UPLOAD
Upload #
Address
Data
1 41 0x085A
2
129[13]
0x0
0x1
3 65 0x28CB
4 66 0x53C6
5 67 0x0344
6 68 0x0085
7 70 0x4820
8 81 0x86A1
9 128 0x460F
10 176 0x00F5
11 180 0x00FD
12 181 0x0144
13 218 0x160B
14 224 0x3E13
15 456 0x0386
16 447 0x0BF1
17 448 0x0BC3
Configure image core
10-bit mode
8-bit mode
Configure CP biasing
Configure AFE biasing
Configure MUX biasing
Configure LVDS biasing
Configure reserved register
Configure reserved register
Configure black calibration
Configure AEC
Configure AEC
Configure AEC
Configure sequencer
Configure sequencer
Configure sequencer
Configure sequencer
Configure sequencer
Description
Soft Power Up
During the soft power up action, the internal blocks are
enabled and prepared to start processing the image data
stream. This action exists of a set of SPI uploads. The soft
power up uploads are listed in Table 9.
Table 9. SOFT POWER UP REGISTER UPLOADS FOR MODE DEPENDENT REGISTERS
Upload #
Address
Data
Description
8-bit mode with PLL
1
32
0x200F
Enable analog clock distribution
2
10
0x0000
Release soft reset state
3
64
0x0001
Enable biasing block
4
72
0x0403
Enable charge pump
5
40
0x0003
Enable column multiplexer
6
48
0x0001
Enable AFE
7
112
0x0007
Enable LVDS transmitters
8-bit mode without PLL
1
32
0x200B
Enable analog clock distribution
2
10
0x0000
Release soft reset state
3
64
0x0001
Enable biasing block
4
72
0x0403
Enable charge pump
5
40
0x0003
Enable column multiplexer
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