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PDF ( 数据手册 , 数据表 ) WS1403

零件编号 WS1403
描述 CDMA PCS 3x3 Power Amplifier Module
制造商 AVAGO
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WS1403 数据手册, 描述, 功能
WS1403
CDMA PCS 3x3 Power Amplifier Module
(1850-1910 MHz)
Data Sheet
Description
The WS1403 is a CDMA Personal Communication Service
(PCS) Power Amplifier (PA), designed for handsets
operating in the 1850~1910 MHz bandwidth.
Digital mode control of CoolPAM reduces current
consumption, which enables extended talk time of
mobile devices.
The WS1403 meets stringent CDMA linearity
requirements to and beyond 28 dBm output power. The
3 mm x 3 mm form factor 8-pin surface mount package
is self contained, incorporating 50 ohm input and output
matching networks.
Features
  Excellent linearity
  Low quiescent current
  High efficiency
  PAE at 28 dBm: 39.8%
  PAE at 17 dBm: 22.3%
  8-pin surface mounting package
  3 mm x 3 mm x 1.0 mm
  Internal 50 ohm matching networks for both RF input
and output
  RoHS compliant
Applications
  Digital CDMA PCS
  Wireless Local loop
Order Information
Functional Block Diagram
Part Number
WS1403-TR1
WS1403-BLK
No. of Devices
1,000
100
Container
7”Tape and Reel
BULK
Vref (1)
Vcont (2)
RF
INPUT
(3)
MMIC
BIAS CIRCUIT & CONTROL LOGIC
INPUT
MATCH
DA
INTER
STAGE
MATCH
PA
Vcc1 (4)
Vcc2 (5)
OUTPUT
MATCH
MODULE
RF
OUTPUT
(6)
Free Datasheet http://www.datasheet4u.com/







WS1403 pdf, 数据表
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
-50
CDG Urban
CDG Suburban
-40 -30
Conventional PAM
-20 -10
0
PA Out (dBm)
10
Digitally Controlled PAM
Figure 13. CDMA power distribution function
700
600
500
400
300
200
100
0
20 30
Cool PAM
Average Current & Talk Time
Probability Distribution Function implies that what is
important for longer talk time is the efficiency of low
or medium power range rather than the efficiency at
full power. WS1403 idle current is 12 mA and operating
current at 17 dBm is 65 mA at nominal condition. This PA
with low current consumption prolongs talk time by no
less than 30 minutes compared to other PAs.
Average current = ∫(PDF x Current)dp
PCB Design Guidelines
The recommended WS1403 PCB land pattern is shown
in Figure 14 and Figure 15. The substrate is coated with
solder mask between the I/O and conductive paddle to
protect the gold pads from short circuit that is caused by
solder bleeding/bridging.
Stencil Design Guidelines
A properly designed solder screen or stencil is required
to ensure optimum amount of solder paste is deposited
onto the PCB pads.
The recommended stencil layout is shown in Figure 16.
Reducing the stencil opening can potentially generate
more voids. On the other hand, stencil openings larger
than 100% will lead to excessive solder paste smear or
bridging across the I/O pads or conductive paddle to
adjacent I/O pads. Considering the fact that solder paste
thickness will directly affect the quality of the solder
joint, a good choice is to use laser cut stencil composed
of 0.100 mm (4 mils) or 0.127 mm (5 mils) thick stainless
steel which is capable of producing the required fine
stencil outline.
0.6
0.4
0.3 mm ON
0.5 mm PITCH
0.7
0.5
0.1
0.55
0.4
1.325
0.6
0.5
1.05
0.8
0.25
Figure 14. Metallization
0.5
0.8
1.4
Figure 15. Solder mask opening
0.8
1.1
Figure 16. Solder paste stencil aperture

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