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PDF ( 数据手册 , 数据表 ) 8S003F3

零件编号 8S003F3
描述 STM8S003F3
制造商 STMicroelectronics
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8S003F3 数据手册, 描述, 功能
STM8S003F3 STM8S003K3
Value line, 16 MHz STM8S 8-bit MCU, 8 Kbyte Flash, 128 byte data
EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C
Datasheet - production data
Features
Core
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Extended instruction set
Memories
Program memory: 8 Kbyte Flash memory; data
retention 20 years at 55 °C after 100 cycles
RAM: 1 Kbyte
Data memory: 128 bytes true data EEPROM;
endurance up to 100 k write/erase cycles
Clock, reset and supply management
2.95 V to 5.5 V operating voltage
Flexible clock control, 4 master clock sources
– Low-power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low-power 128 kHz RC
Clock security system with clock monitor
Power management
– Low-power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
– Permanently active, low-consumption
power-on and power-down reset
Interrupt management
Nested interrupt controller with 32 interrupts
Up to 27 external interrupts on 6 vectors
LQFP32
7x7 mm
TSSOP20
6.5x6.4 mm
UFQFPN20
3x3 mm
Timers
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
16-bit general purpose timers, with 3 CAPCOM
channels (IC, OC or PWM)
8-bit basic timer with 8-bit prescaler
Auto wakeup timer
Window and independent watchdog timers
Communications interfaces
UART with clock output for synchronous
operation, SmartCard, IrDA, LIN master mode
SPI interface up to 8 Mbit/s
I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
10-bit ADC, ± 1 LSB ADC with up to 5
multiplexed channels, scan mode and analog
watchdog
I/Os
Up to 28 I/Os on a 32-pin package including 21
high-sink outputs
Highly robust I/O design, immune against
current injection
Development support
Embedded single-wire interface module
(SWIM) for fast on-chip programming and non-
intrusive debugging
April 2016
This is information on a product in full production.
DocID018576 Rev 8
1/103
www.st.com







8S003F3 pdf, 数据表
List of figures
STM8S003F3 STM8S003K3
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
UFQFPN20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
STM8S003F3/K3 value line ordering information scheme(1) . . . . . . . . . . . . . . . . . . . . . . . 99
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DocID018576 Rev 8







8S003F3 equivalent, schematic
Product overview
STM8S003F3 STM8S003K3
4.6 Power management
For efficient power management, the application can be put in one of four different low-
power modes. You can configure each mode to obtain the best compromise between the
lowest power consumption, the fastest start-up time and available wakeup sources.
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
4.7 Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2. Refresh out of window: the down-counter is refreshed before its value is lower than the
one stored in the window register.
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DocID018576 Rev 8










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