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PDF ( 数据手册 , 数据表 ) ADRF6518

零件编号 ADRF6518
描述 Dual Programmable Filters and Variable Gain Amplifiers
制造商 Analog Devices
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ADRF6518 数据手册, 描述, 功能
Preliminary Technical Data
63 MHz Dual Programmable Filters and
Variable Gain Amplifiers
ADRF6518
FEATURES
Matched pair of programmable filters and triple VGAs
Continuous gain control range: 72 dB
Digital gain control: 30 dB
6-pole Butterworth filter: 1 MHz to 63 MHz
in 1 MHz steps, 1 dB corner frequency
Preamplifier and postamplifier gain steps
Peak detector
Filter bypass mode, −3 dB bandwidth (BW)
VGA2 and VGA3 21 dB/12 dB gain: 350 MHz/700 MHz
IMD3: >65 dBc for 1.5 V p-p composite output
HD2, HD3: >65 dBc for 1.5 V p-p output
Differential input and output
Flexible output and input common-mode ranges
Optional dc output offset correction
SPI programmable filter corners and gain steps
Single 3.3 V supply operation with power-down feature
APPLICATIONS
Baseband I/Q receivers
Diversity receivers
ADC drivers
Point-to-point and point-to-multipoint radios
Instrumentation
Medical
GENERAL DESCRIPTION
The ADRF6518 is a matched pair of fully differential low noise and
low distortion programmable filters and variable gain amplifiers
(VGAs). Each channel is capable of rejecting large out-of-band
interferers while reliably boosting the wanted signal, thus reducing
the bandwidth and resolution requirements on the analog-to-
digital converters (ADCs). The excellent matching between
channels and their high spurious-free dynamic range over all
gain and bandwidth settings make the ADRF6518 ideal for
quadrature-based (IQ) communication systems with dense
constellations, multiple carriers, and nearby interferers. The
various amplifier gains, filter corners and other features are all
programmable via a serial port interface (SPI) port.
The first VGA that precedes the filters offers 24 dB of continuous
gain control with fixed gain options of 9 dB, 12 dB, and 15 dB, and
sets a differential input impedance of 400 Ω. The filters provide
a six-pole Butterworth response with 1 dB corner frequencies
from 1 MHz to 63 MHz in 1 MHz steps. For operation beyond
63 MHz, the filter can be disabled and completely bypassed via
the SPI. A wideband peak detector is available to monitor the
FUNCTIONAL BLOCK DIAGRAM
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Figure 1.
peak signal at the filter inputs. The pair of VGAs that follow the
filters each provides 24 dB of continuous gain control with fixed
gain options of 12 dB, 15 dB, 18 dB, and 21 dB. The output buffers
offer an additional option of 3 dB or 9 dB gain and provide a
differential output impedance of less than 10 Ω. They are
capable of driving 3 V p-p into 1 kΩ loads at better than 65 dBc
HD3. The output common-mode voltage defaults to VPS/2 and
can be adjusted down to 900 mV by driving the high impedance
VOCM pin. Independent, built-in dc offset correction loops for
each channel can be disabled via the SPI if fully dc-coupled
operation is desired. The high-pass corner frequency is deter-
mined by external capacitors on the OFS1 and OFS2 pins and the
postfilter VGA gain.
The ADRF6518 operates from a 3.15 V to 3.45 V supply and
consumes a maximum supply current of 400 mA. When fully
disabled, it consumes <10 mA. The ADRF6518 is fabricated in
an advanced silicon-germanium BiCMOS process and is available
in a 32-lead, exposed pad LFCSP. Performance is specified over
the −40°C to +85°C temperature range.
Rev. PrA
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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ADRF6518 pdf, 数据表
ADRF6518
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
FILTER MODE
VPS = 3.3 V, TA = 25°C, ZLOAD = 400 Ω, low power mode, digital gain code B[8:2] = 1111110, and B1 = 0, unless otherwise noted.
Figure 5. In-Band Gain vs. VGN1 over Supply and Temperature
(BW Setting = 63 MHz)
Figure 8. Gain Conformance vs. VGN1 over Supply and Temperature
(Bandwidth Setting = 63 MHz)
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Figure 6. In-Band Gain vs. VGN2 over Supply and Temperature
(BW Setting = 63 MHz)
Figure 9. Gain Conformance vs. VGN2 over Supply and Temperature
(Bandwidth Setting = 63 MHz)
Figure 7. In-Band Gain vs. VGN3 over Supply and Temperature
(BW Setting = 63 MHz)
Figure 10. Gain Conformance vs. VGN3 over Supply and Temperature
(Bandwidth Setting = 63 MHz)
Rev. PrA | Page 8 of 36
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ADRF6518 equivalent, schematic
ADRF6518
Preliminary Technical Data
BYPASS MODE
VPS = 3.3 V, TA = 25°C, ZLOAD = 400 Ω, High Power mode, digital gain code B8:B2 = 1111110, and B1 = 0 unless otherwise noted.
Figure 48. Frequency Response over Supply and Temperature
Figure 51. Channel Isolation (OUTA to OUTB) vs. Frequency
Figure 49. Group Delay vs. Frequency
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Figure 52. Noise Figure vs. Analog Gain over Digital Gain
Figure 50. Output Noise Density vs. Frequency over Analog Gains;
Digital Gain = 0000001
Figure 53. Output Noise Density vs. Analog Gain over Digital Gain
Rev. PrA | Page 16 of 36
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