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PDF ( 数据手册 , 数据表 ) 7851

零件编号 7851
描述 AD7851
制造商 Analog Devices
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7851 数据手册, 描述, 功能
a
14-Bit 333 kSPS
Serial A/D Converter
AD7851
FEATURES
Single 5 V Supply
333 kSPS Throughput Rate/؎2 LSB DNL—A Grade
285 kSPS Throughput Rate/؎1 LSB DNL—K Grade
A & K Grades Guaranteed to 125؇C/238 kSPS
Throughput Rate
Pseudo-Differential Input with Two Input Ranges
System and Self-Calibration with Autocalibration on
Power-Up
Read/Write Capability of Calibration Data
Low Power: 60 mW typ
Power-Down Mode: 5 W typ Power Consumption
Flexible Serial Interface:
8051/SPI/QSPI/ P Compatible
24-Pin DIP, SOIC and SSOP Packages
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
Instrumentation and Control Systems
High Speed Modems
Automotive
AIN (+)
AIN (–)
REFIN/
REFOUT
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
AGND
T/H
4.096 V
REFERENCE
BUF
AD7851
COMP
DVDD
DGND
AMODE
CREF1
CREF2
CAL
CHARGE
REDISTRIBUTION
DAC
CALIBRATION
MEMORY
AND CONTROLLER
SAR + ADC
CONTROL
CLKIN
CONVST
BUSY
SLEEP
SERIAL INTERFACE / CONTROL REGISTER
SM1 SM2 SYNC DIN DOUT SCLK POLARITY
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GENERAL DESCRIPTION
The AD7851 is a high speed, 14-bit ADC that operates from a
single 5 V power supply. The ADC powers-up with a set of
default conditions at which time it can be operated as a read-
only ADC. The ADC contains self-calibration and system-
calibration options to ensure accurate operation over time and
temperature and has a number of power-down options for low
power applications.
PRODUCT HIGHLIGHTS
1. Single 5 V supply.
2. Operates with reference voltages from 4 V to VDD.
3. Analog input ranges from 0 V to VDD.
4. System and self-calibration including power-down mode.
5. Versatile serial I/O port.
The AD7851 is capable of 333 kHz throughput rate. The input
track-and-hold acquires a signal in 0.33 µs and features a
pseudo-differential sampling scheme. The AD7851 has the
added advantage of two input voltage ranges (0 V to VREF, and
–VREF/2 to +VREF/2 centered about VREF/2). Input signal range
is to VDD and the part is capable of converting full-power signals
to 20 MHz.
CMOS construction ensures low power dissipation (60 mW typ)
with power-down mode (5 µW typ). The part is available in 24-
pin, 0.3 inch-wide dual-in-line package (DIP), 24-lead small
outline (SOIC) and 24-lead small shrink outline (SSOP) packages.
*Patent pending.
See Page 35 for data sheet index.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
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7851 pdf, 数据表
AD7851
Pin Mnemonic
1 CONVST
2 BUSY
3 SLEEP
4 REFIN/
REFOUT
5 AVDD
6, 12 AGND
7 CREF1
8 CREF2
9 AIN(+)
10 AIN(–)
11 NC
13 AMODE
14 POLARITY
15 SM1
16 SM2
17 CAL
18 DVDD
19 DGND
20 DOUT
21 DIN
22 CLKIN
23 SCLK
24 SYNC
Description
PIN FUNCTION DESCRIPTION
Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and
starts conversion. When this input is not used, it should be tied to DVDD.
Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL, and
remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed
its on-chip calibration sequence.
Sleep Input/Low Power Mode. A logic 0 initiates a sleep and all circuitry is powered down including the in-
ternal voltage reference provided there is no conversion or calibration being performed. Calibration data is
retained. A logic 1 results in normal operation. See Power-Down section for more details.
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this ap-
pears at the pin. This pin can be overdriven by an external reference or can be taken as high as AVDD.
When this pin is tied to AVDD, then the CREF1 pin should also be tied to AVDD.
Analog Positive Supply Voltage, +5.0 V ± 5%.
Analog Ground. Ground reference for track/hold, reference and DAC.
Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). This external capacitor is
used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND.
Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). This external capacitor is
used in conjunction with the on-chip reference. The capacitor should be tied between the pin and AGND.
Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above
AVDD at any time, and cannot go below AIN(–) when the unipolar input range is selected.
Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above
AVDD at any time.
No Connect Pin.
Analog Mode Pin. This pin allows two different analog input ranges to be selected. A logic 0 selects range 0
to VREF (i.e., AIN(+) – AIN(–) = 0 to VREF). In thishttp://www.DataSheet4U.net/ case AIN(+) cannot go below AIN(–) and
AIN(–) cannot go below AGND. A logic 1 selects range –VREF/2 to +VREF/2 (i.e., AIN(+) – AIN(–) =
–VREF /2 to +VREF/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to
+VREF/2 to allow AIN(+) to go from 0 V to +VREF V.
Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will
reverse the active edge of the serial clock (SCLK). A logic 1 means that the serial clock (SCLK) idles high
and a logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and
Table X for the SCLK active edges.
Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-
tion as described in Table XI.
Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-
tion as described in Table XI.
Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A logic 0 on this pin resets all
logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF capacitor from
this pin to AGND to allow for an automatic self calibration on power-up. This input overrides all other
internal operations.
Digital Supply Voltage, +5.0 V ± 5%.
Digital Ground. Ground reference point for digital circuitry.
Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act
as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table XI).
Master Clock Signal for the device (6 MHz or 7 MHz). Sets the conversion and calibration times.
Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the
type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and
SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.
This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync
in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table XI).
–8–
REV. A
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7851 equivalent, schematic
AD7851
Input Ranges
The analog input range for the AD7851 is 0 V to VREF in both
the unipolar and bipolar ranges.
The only difference between the unipolar range and the bipolar
range is that in the bipolar range the AIN(–) has to be biased up
to +VREF/2 and the output coding is 2s complement (See Table
V and Figures 14 and 15). The unipolar or bipolar mode is se-
lected by the AMODE pin (0 for the unipolar range and 1 for
the bipolar range).
Table V. Analog Input Connections
Analog Input Input Connections Connection
Range
AIN(+) AIN(–) Diagram AMODE
0 V to VREF1
± VREF/22
VIN
VIN
AGND Figure 8
VREF/2 Figure 9
DGND
DVDD
NOTES
1Output code format is straight binary.
2Range is ± VREF/2 biased about VREF/2. Output code format is 2s complement.
Note that the AIN(–) pin on the AD7851 can be biased up
above AGND in the unipolar mode also, if required. The ad-
vantage of biasing the lower end of the analog input range away
from AGND is that the user does not have to have the analog
input swing all the way down to AGND. This has the advantage
in true single supply applications that the input amplifier does
not have to swing all the way down to AGND. The upper end of
the analog input range is shifted up by the same amount. Care
must be taken so that the bias applied does not shift the upper
end of the analog input above the AVDD supply. In the case
where the reference is the supply, AVDD, the AIN(–) must be
tied to AGND in unipolar mode.
VIN = 0 TO VREF
UNIPOLAR
ANALOG
INPUT RANGE
SELECTED
AIN(+)
AIN(–)
AMODE
TRACK AND HOLD
AMPLIFIER
DOUT
STRAIGHT
BINARY
FORMAT
AD7851
Figure 14. 0 V to VREF Unipolar Input Configuration
Transfer Functions
For the unipolar range the designed code transitions occur mid-
way between successive integer LSB values (i.e., 1/2 LSB,
3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is
straight binary for the unipolar range with 1 LSB = FS/16384 =
4.096 V/16384 = 0.25 mV when VREF = 4.096 V. The ideal in-
put/output transfer characteristic for the unipolar range is shown
in Figure 16.
OUTPUT
CODE
111...111
111...110
111...101
111...100
000...011
000...010
FS
1LSB =
16384
000...001
000...000
0V 1LSB
+FS –1LSB
VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE
Figure 16. AD7851 Unipolar Transfer Characteristic
Figure 15 shows the AD7851’s ± VREF/2 bipolar analog input
configuration (where AIN(+) cannot go below 0 V so for the full
bipolar range then the AIN(–) pin should be biased to +VREF/2).
Once again the designed code transitions occur midway between
successive integer LSB values. The output coding is 2s comple-
ment with 1 LSB = 16384 = 4.096 V/16384 = 0.25 mV. The
ideal input/output transfer characteristic is shown in
Figure 17.
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OUTPUT
CODE
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
(VREF/2) –1 LSB
0V
+ FS – 1 LSB
(VREF/2) +1 LSB
FS = VREFV
1LSB = FS
16384
VREF/2
VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE
Figure 17. AD7851 Bipolar Transfer Characteristic
VIN = 0 TO VREF
VREF/2
DVDD
UNIPOLAR
ANALOG
INPUT RANGE
SELECTED
AIN(+)
AIN(–)
AMODE
TRACK AND HOLD
AMPLIFIER
DOUT
2S
COMPLEMENT
FORMAT
AD7851
Figure 15. ±VREF/2 about VREF/2 Bipolar Input Configuration
–16–
REV. A
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