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PDF ( 数据手册 , 数据表 ) UBA2071

零件编号 UBA2071
描述 Half bridge control IC
制造商 NXP Semiconductors
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UBA2071 数据手册, 描述, 功能
UBA2071; UBA2071A
Half bridge control IC for CCFL backlighting
Rev. 01 — 23 June 2008
Product data sheet
1. General description
2. Features
The UBA2071 and UBA2071A are high voltage ICs intended to drive Cold Cathode
Fluorescent Lamps (CCFLs) or External Electrode Fluorescent Lamps (EEFLs) for
backlighting applications. They can drive a half bridge circuit made up of two NMOSFETs
with a supply voltage of up to 550 V, so the inverter can be supplied directly from a 400 V
PFC bus.
The UBA2071 and UBA2071A contain a controller, a level shifter, a bootstrap diode and
drivers for the external half bridge power switches. It also contains a low frequency PWM
generator, which can be used to control the brightness level of the lamps, using an analog
brightness/dimming control voltage. PWM dimming can also be realized, using a digital
PWM input signal. PWM dimming can be synchronized with other ICs. The lamp current is
controlled by means of a true zero voltage switching resonant control principle, ensuring
lowest possible switch losses in the half bridge power structure.
The UBA2071 is designed to be supplied by a V/t supply from the half bridge circuit that
it drives. The IC itself needs little current and if the IC is off, a clamp protects the supply
voltage from getting too high.
The UBA2071A is designed to be supplied by a fixed 12 V supply. It has a lower supply
start voltage and no supply clamp.
http://www.DataSheet4U.net/
I Suitable for operating in a very wide inverter supply voltage range (up to 550 V DC).
I Integrated level shifter.
I Integrated bootstrap diode.
I Lamp current control by means of a true zero voltage switching resonant control
principle.
I Sample & Hold circuit, maintaining current control value during PWM lamp-off
situation.
I Separately definable time constants for current control loop and PWM dimming
attack/decay setting.
I Overvoltage control.
I Overcurrent protection.
I Ignition failure detection.
I Hard switching control.
I Arcing detection.
I Open/short pin protections on feedback pins.
I Integrated, programmable fault timer.
datasheet pdf - http://www.DataSheet4U.net/







UBA2071 pdf, 数据表
NXP Semiconductors
UBA2071; UBA2071A
Half bridge control IC for CCFL backlighting
8.2 VDD clamp
When the UBA2071 is disabled (EN pin low) or in the stop state, the VDD clamp is
activated. The VDD clamp is an internal active zener limiting the voltage to Vclamp(VDD). It
prevents the start-up current source from charging the VDD buffer capacitor to too high a
voltage.
The maximum current that is allowed to be delivered by the start-up current source is
determined by the clamp voltage as stated in Table 6 and the maximum allowed VDD
voltage as stated in Table 4.
The UBA2071A has no VDD clamp.
8.3 Enable
The UBA2071 or UBA2071A can be activated or set to standby via the EN pin. If the
voltage on the EN pin is below Vth(L)(EN), the IC will stop oscillating at the next GL high
state2, and most parts of the internal circuits will shut down. When the EN pin is left open,
it is pulled low by an internal bias current of Ibias(EN).
When the voltage on the EN pin comes above Vth(H)1(EN), the IC will start up in
DC blocking capacitor charging mode (see Section 8.8). When the voltage on the EN pin
goes over Vth(H)2(EN), the IC will start with the initial ignition frequency sweep (see
Section 8.8) and subsequently go to normal operation mode again.
8.4 The oscillator
The UBA2071 and UBA2071A have anhttp://www.DataSheet4U.net/ internal voltage controlled sawtooth oscillator, see
Figure 5. Its frequency inverses in proportion to the capacitor connected to the CF pin.
The IC switches GL on and GH off during one oscillator period and GL off and GH on
during the next oscillator period. This results in a half bridge voltage with a frequency
(called the switching frequency fsw from here on) of half the oscillator frequency and with a
duty cycle of exactly 50 %.
The oscillator frequency is controlled by changing the charge current at the CF pin. By
changing the frequency the lamp current is controlled. It is also used to limit the
transformer output voltage and for gradually switching the lamps on and off during PWM
dimming.
2. When both GH and GL are low during the lamps off period of PWM dimming (so PWMD is high), the IC will wait with entering the
standby state until PWMD becomes low again and GL can be made high.
UBA2071_A_1
Product data sheet
Rev. 01 — 23 June 2008
© NXP B.V. 2008. All rights reserved.
8 of 35
datasheet pdf - http://www.DataSheet4U.net/







UBA2071 equivalent, schematic
NXP Semiconductors
UBA2071; UBA2071A
Half bridge control IC for CCFL backlighting
PWM lamp-on situation is reached again through a reverse sequence of events, starting
the half bridge actions, increasing the voltage on CSWP, increasing the lamp current back
to the controlled value. Switch S1 is closed (conducting) again when the voltage on the
CSWP pin has reached the voltage on the CVFB pin again.
The IC waits until the CSWP sweep-up6 has reached the current/voltage control level at
the CVFB pin before sweeping down. This prevents the lamps from going out completely
when deep dimming on CSWP pin is combined with a large value capacitor.
After the switching frequency has reached fsw(max), both GL and GH are made low, so both
half bridge powers will be non-conducting, see Figure 12. This guarantees zero lamp
current during the PWM-off period7, while the CSWP frequency sweep acts as soft stop
and soft restart, of which the softness can be set by the value of the capacitor connected
to the CSWP pin.
max
reg
VCSWP
0
t
5V
VPWMD
0
VDD
VGH VSH
0
VDD
VGL
http://www.DataSheet4U.net/
t
t
0
Fig 12. PWM dim cycle waveforms
t
014aaa107
Three pins are available to configure the internal PWM generator: the CPWM pin, PWMA
pin, and the PWMD pin. The two possible PWM configurations are shown in Figure 13. In
the analog or master mode the internal PWM generator is active and generating the PWM
signal. This signal is put on the PWMD pin, which is automatically configured as an
output. The minimum duty cycle of the internal PWM generator is limited to δPWM(min).
6. CSWP sweep-up is frequency sweep-down.
7. Until the ringing of voltage on the half bridge point has died away, some (capacitive) current may still cause a light glow at the hot
side of the lamps. Therefore it is advised to maximize the attenuation of the ringing circuit (made up by the transformer inductance
and the V/t limiting capacitor).
UBA2071_A_1
Product data sheet
Rev. 01 — 23 June 2008
© NXP B.V. 2008. All rights reserved.
16 of 35
datasheet pdf - http://www.DataSheet4U.net/










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