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PDF ( 数据手册 , 数据表 ) AD5144

零件编号 AD5144
描述 (AD5124 / AD5144) Nonvolatile Digital Potentiometer
制造商 Analog Devices
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AD5144 数据手册, 描述, 功能
Data Sheet
Quad Channel, 128-/256-Position, I2C/SPI,
Nonvolatile Digital Potentiometer
AD5124/AD5144/AD5144A
FEATURES
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: ±6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
Fast start-up time < 75 µs
Linear gain setting mode
Single- and dual-supply operation
Independent logic supply: 1.8 V to 5.5 V
Wide operating temperature: −40°C to +125°C
4 mm × 4 mm package option
4 kV ESD protection
APPLICATIONS
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VDD
LRDAC
POWER-ON
RESET
AD5124/AD5144
RDAC1
INPUT
REGISTER 1
RESET
DIS
SCLK/SCL
SDI/SDA
SYNC/ADDR0
SDO/ADDR1
SERIAL
INTERFACE 7/8
RDAC2
INPUT
REGISTER 2
RDAC3
INPUT
REGISTER 3
RDAC4
INPUT
REGISTER 4
EEPROM
MEMORY
A1
W1
B1
A2
W2
B2
A3
W3
B3
A4
W4
B4
GND VSS
WP
Figure 1. AD5124/AD5144 24-Lead LFCSP
GENERAL DESCRIPTION
The AD5124/AD5144/AD5144A potentiometers provide a
nonvolatile solution for 128-/256-position adjustment applications,
offering guaranteed low resistor tolerance errors of ±8% and up to
±6 mA current density in the Ax, Bx, and Wx pins.
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through the RAW and RWB string resistors, allowing very accurate
resistor matching.
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making these devices
suitable for filter design.
The low wiper resistance of only 40 Ω at the ends of the resistor
array allow for pin-to-pin connection.
The wiper values can be set through an SPI-/I2C-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
www.DataSheet.net/ The AD5124/AD5144/AD5144A are available in a compact,
24-lead, 4 mm × 4 mm LFCSP and a 20-lead TSSOP. The parts
are guaranteed to operate over the extended industrial temperature
range of −40°C to +125°C.
Table 1. Family Models
Model
Channel Position
AD51231 Quad
128
AD5124 Quad
128
AD5124 Quad
128
AD51431 Quad
256
AD5144 Quad
256
AD5144 Quad
256
AD5144A Quad
256
AD5122 Dual
128
AD5122A Dual
128
AD5142 Dual
256
AD5142A Dual
256
AD5121 Single
128
AD5141 Single
256
Interface
I2C
SPI/I2C
SPI
I2C
SPI/I2C
SPI
I2C
SPI
I2C
SPI
I2C
SPI/I2C
SPI/I2C
Package
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
LFCSP
1 Two potentiometers and two rheostats.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Datasheet pdf - http://www.DataSheet4U.co.kr/







AD5144 pdf, 数据表
AD5124/AD5144/AD5144A
Parameter
RESISTOR TERMINALS
Maximum Continuous Current
Symbol
IA, IB, and IW
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
Capacitance W3
CW
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
High
Low
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
Positive Supply Current
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Logic Supply Current
Power Dissipation8
Power Supply Rejection Ratio
VINH
VINL
VHYST
IIN
CIN
VOH
VOL
IDD
ISS
IDD_EEPROM_STORE
IDD_EEPROM_READ
ILOGIC
PDISS
PSRR
Test Conditions/Comments Min
Data Sheet
Typ1 Max
Unit
RAB = 10 kΩ
RAB = 100 kΩ
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
−6
−1.5
VSS
−500
+6
+1.5
VDD
25
12
12
5
±15 +500
mA
mA
V
pF
pF
pF
pF
nA
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
RPULL-UP = 2.2 kΩ to VLOGIC
ISINK = 3 mA
ISINK = 6 mA, VLOGIC > 2.3 V
www.DataSheet.net/
VSS = GND
Single supply, VSS = GND
Dual supply, VSS < GND
VIH = VLOGIC or VIL = GND
VDD = 5.5 V
VDD = 2.3 V
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
∆VDD/∆VSS = VDD ± 10%,
code = full scale
0.8 × VLOGIC
0.7 × VLOGIC
0.1 × VLOGIC
5
0.2 × VLOGIC
±1
V
V
V
V
µA
pF
VLOGIC
0.4
V
V
0.6 V
−1 +1 µA
2 pF
2.3
±2.25
1.8
2.25
−5.5
5.5
±2.75
VDD
VDD
0.7 5.5
400
−0.7
2
320
1 120
3.5
−66 −60
V
V
V
V
µA
nA
µA
mA
µA
nA
µW
dB
Rev. 0 | Page 8 of 36
Datasheet pdf - http://www.DataSheet4U.co.kr/







AD5144 equivalent, schematic
AD5124/AD5144/AD5144A
Data Sheet
GND 1
A1 2
W1 3
B1 4
A3 5
W3 6
PIN 1
INDICATOR
AD5124/
AD5144
TOP VIEW
(Not to Scale)
18 DIS
17 SCL/SCLK
16 VLOGIC
15 VDD
14 B4
13 W4
NOTES
1. INTERNALLY CONNECT THE
EXPOSED PAD TO VSS.
Figure 11. 24-Lead LFCSP Pin Configuration (AD5124/AD5144)
Table 11. 24-Lead LFCSP Pin Function Descriptions (AD5124/AD5144)
Pin No. Mnemonic Description
1 GND
Ground Pin, Logic Ground Reference.
2 A1
Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
3 W1
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
4 B1
Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
5 A3
Terminal A of RDAC3. VSS ≤ VA ≤ VDD.
6 W3
Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD.
7 B3
Terminal B of RDAC3. VSS ≤ VB ≤ VDD.
8 VSS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
9 A2
Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
www.DataSheet.net/
10 W2
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
11 B2
Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
12 A4
Terminal A of RDAC4. VSS ≤ VA ≤ VDD.
13 W4
Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD.
14 B4
Terminal B of RDAC4. VSS ≤ VB ≤ VDD.
15 VDD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
16 VLOGIC
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
17
SCL/SCLK
I2C Serial Clock Line (SCL). Data is clocked in at the logic low transition.
SPI Serial Clock Line (SCLK). Data is clocked in at the logic low transition.
18 DIS
Digital Interface Select (SPI/I2C Select). SPI when DIS = 0 (GND), and I2C when DIS = 1 (VLOGIC). This pin cannot be
left floating.
19 SDA/SDI Serial Data Input/Output (SDA), When DIS = 1.
Serial Data Input (SDI), When DIS = 0.
20 WP
Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM content, except when
reloading the content of the EEPROM into the RDAC register. WP is activated at logic low. If this pin is not used,
tie WP to VLOGIC.
21 ADDR1/SDO Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1.
Serial Data Output (SDO). Open-drain output, needs an external pull-up resistor, when DIS = 0.
22 ADDR0/SYNC Programmable Address (ADDR0) for Multiple Package Decoding, When DIS = 1.
Synchronization Data Input, When DIS = 0. This pin is active low. When SYNC returns high, data is loaded into
the input shift register.
23 LRDAC
24 RESET
EPAD
Load RDAC. Transfers the contents of the input registers to their respective RDAC registers when their
associated input registers were previously loaded using Command 2 (see Table 20). This allows simultaneous
update of all RDAC registers. LRDAC is activated at the high-to-low transition. If not used, tie LRDAC to VLOGIC.
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If not used,
tie RESET to VLOGIC.
Internally Connect the Exposed Pad to VSS.
Rev. 0 | Page 16 of 36
Datasheet pdf - http://www.DataSheet4U.co.kr/










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