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PDF ( 数据手册 , 数据表 ) Z16F2810

零件编号 Z16F2810
描述 High Performance Microcontrollers
制造商 Zilog
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Z16F2810 数据手册, 描述, 功能
High Performance Microcontrollers
ZNEO® Z16F Series
Product Specification
PS022007-0109
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Copyright ©2009 by Zilog®, Inc. All rights reserved.
www.zilog.com
Datasheet pdf - http://www.DataSheet4U.co.kr/







Z16F2810 pdf, 数据表
ZNEO® Z16F Series
Product Specification
vii
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 90
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 92
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Reading Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Timer 0-2 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Timer X Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . 107
Timer 0-2 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . 108
Timer 0-2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Multi-Channel PWM Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
PWM Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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PWM Reload Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PWM Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PWM Period and Count Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PWM Duty Cycle Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Independent and Complementary PWM Outputs . . . . . . . . . . . . . . . . . . . 118
Manual Off-state Control of PWM Output Channels . . . . . . . . . . . . . . . . . 119
Deadband Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Minimum PWM Pulse Width Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Synchronization of PWM and ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Synchronized Current-Sense Sample and Hold . . . . . . . . . . . . . . . . . . . . 120
PWM Timer and Fault Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Fault Detection and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PWM Operation in CPU HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PWM Operation in CPU STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Observing the State of PWM Output Channels . . . . . . . . . . . . . . . . . . . . . 121
PWM Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PWM Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . 122
PWM 0-2 Duty Cycle High and Low Byte Registers . . . . . . . . . . . . . . . . . 123
PS022007-0109
PRELIMINARY
Table of Contents
Datasheet pdf - http://www.DataSheet4U.co.kr/







Z16F2810 equivalent, schematic
ZNEO® Z16F Series
Product Specification
1
Introduction
Zilog’s ZNEO® Z16F family of products are optimized for demanding applications.
The ZNEO line of Zilog® microcontroller products are based on the new ZNEO CPU.
Features
ZNEO family of products include the following features:
20 MHz ZNEO CPU
128 KB internal Flash memory with 16-bit access and In-Circuit Programming (ICP)
4 KB internal RAM with 16-bit access
External interface allows seamless connection to external data memory and
peripheral with:
– Six chip selects with programmable Wait states
– 24-bit address bus supports 16 MB
– Selectable 8-bit or 16-bit data bus widths
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– Programmable chip select signal polarity
– ISA-compatible mode
12-channel, 10-bit Analog-to-Digital Converter (ADC)
Operational Amplifier
Analog Comparator
4-channel Direct Memory Access (DMA) controller supports internal or
external DMA requests
Two full-duplex 9-bit Universal Asynchronous Receiver/Transmitter (UARTs) with
support for Local Interconnect Network (LIN) and Infrared Data Association (IrDA)
Internal Precision Oscillator (IPO)
Inter-Integrated Circuit (I2C) master/slave controller
Enhanced Serial Peripheral Interface (ESPI)
12-bit Pulse Width Modulation (PWM) module with three complementary pairs or
six independent PWM outputs with deadband generation and fault trip input
Three standard 16-bit timers with Capture, Compare, and PWM capability
Watchdog Timer (WDT) with internal RC oscillator
76 General-Purpose Input/Output (GPIO) pins
PS022007-0109
PRELIMINARY
Introduction
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