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PDF ( 数据手册 , 数据表 ) 92HD92

零件编号 92HD92
描述 SINGLE CHIP PC AUDIO SYSTEM
制造商 IDT
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92HD92 数据手册, 描述, 功能
DATASHEET
SINGLE CHIP PC AUDIO SYSTEM
CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO+I2S
Description
The 92HD92 single-chip audio system is a low power
optimized, high fidelity, 4-channel audio codec with
integrated speaker amplifier, capless headphone amplifier,
and low drop out voltage regulator.
Dual High Definition Audio and I2S Interfaces allow for
docking and secondary audio support with a single codec.
The integrated combo jack allows for dual-function
headphone and headset detection.
The integrated high-pass and band-pass filters allow for
Hardware EQ and speaker protection.
The high integration of the 92HD92 enables the smallest
PCB footprint with the lowest system audio BOM count and
cost.
The 92HD92 provides high quality HD Audio capability to
notebook and business desktop PC applications.
92HD92
Features
• 4 Channels (2 stereo DACs and 2 stereo ADCs)
with 24-bit resolution
• Supports full-duplex stereo audio and simultaneous
VoIP
• Provides a mono output
• 2.1 audio crossover support
• 2W/channel Class-D stereo BTL speaker amplifier
@ 4 ohms and 5V
• 10 band hardware parametric equalizer
• Hardware compressor limiter
• Capless headphone amplifier with charge
pump/LDO
• I2S support (2 input, 1 output)
• Aux Audio Mode with I2C
• Combo Jack Support allowing for dual-function
headphone and headset detection
• Speaker Protection
• Dedicated BTL high pass filter
• Mono bandpass filter
• Full HDA015-B low power support
www.DataSheet.net/ Internal digital core LDO voltage regulator
• Microsoft WLP desktop premium logo compliant
• Dual SPDIF for WLP compliant support of
simultaneous HDMI and SPDIF output
• Support for 1.5V and 3.3V HDA signaling
• Two digital microphone inputs (mono, stereo, or
quad microphones)
• High performance analog mixer
• 2 adjustable VREF Out pins for analog microphone
bias
• 3 analog ports with port presence detect (2 single
ended, 1 BTL)
• Digital PC Beep support
• 48-pad QFN RoHS package
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
1
V 1.1 1/12
92HD92
Datasheet pdf - http://www.DataSheet4U.co.kr/







92HD92 pdf, 数据表
92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
7.24.2. SPDIFOut0 (NID = 1Dh): StreamCap ............................................................................260
7.24.3. SPDIFOut0 (NID = 1Dh): OutAmpCap ...........................................................................260
7.24.4. SPDIFOut0 (NID = 1Dh): Cnvtr ......................................................................................261
7.24.5. SPDIFOut0 (NID = 1Dh): OutAmpLeft ...........................................................................262
7.24.6. SPDIFOut0 (NID = 1Dh): OutAmpRight .........................................................................263
7.24.7. SPDIFOut0 (NID = 1Dh): PwrState ................................................................................263
7.24.8. SPDIFOut0 (NID = 1Dh): CnvtrID ..................................................................................264
7.24.9. SPDIFOut0 (NID = 1Dh): DigCnvtr ................................................................................265
7.25. SPDIFOut1 (NID = 1Eh): WCap ..................................................................................................266
7.25.1. SPDIFOut1 (NID = 1Eh): PCMCap ................................................................................267
7.25.2. SPDIFOut1 (NID = 1Eh): StreamCap ............................................................................269
7.25.3. SPDIFOut1 (NID = 1Eh): OutAmpCap ...........................................................................269
7.25.4. SPDIFOut1 (NID = 1Eh): Cnvtr ......................................................................................270
7.25.5. SPDIFOut1 (NID = 1Eh): OutAmpLeft ...........................................................................271
7.25.6. SPDIFOut1 (NID = 1Eh): OutAmpRight .........................................................................272
7.25.7. SPDIFOut1 (NID = 1Eh): PwrState ................................................................................272
7.25.8. SPDIFOut1 (NID = 1Eh): CnvtrID ..................................................................................273
7.25.9. SPDIFOut1 (NID = 1Eh): DigCnvtr .................................................................................274
7.26. Dig0Pin (NID = 1Fh): WCap ........................................................................................................275
7.26.1. Dig0Pin (NID = 1Fh): PinCap .........................................................................................276
7.26.2. Dig0Pin (NID = 1Fh): ConLst .........................................................................................277
7.26.3. Dig0Pin (NID = 1Fh): ConLstEntry0 ...............................................................................278
7.26.4. Dig0Pin (NID = 1Fh): PwrState ......................................................................................278
7.26.5. Dig0Pin (NID = 1Fh): PinWCntrl ....................................................................................279
7.26.6. Dig0Pin (NID = 1Fh): UnsolResp ..................................................................................280
7.26.7. Dig0Pin (NID = 1Fh): ChSense ......................................................................................280
7.26.8. Dig0Pin (NID = 1Fh): ConfigDefault ...............................................................................281
7.27. Dig1Pin (NID = 20h): WCap .........................................................................................................283
7.27.1. Dig1Pin (NID = 20h): PinCap .........................................................................................285
7.27.2. Dig1Pin (NID = 20h): ConLst .........................................................................................286
7.27.3. Dig1Pin (NID = 20h): ConLstEntry0 ..........www..DataS.heet..net/.................................................................. 287
7.27.4. Dig1Pin (NID = 20h): PwrState ......................................................................................287
7.27.5. Dig1Pin (NID = 20h): PinWCntrl .....................................................................................288
7.27.6. Dig1Pin (NID = 20h): ConfigDefault ...............................................................................289
7.28. DigBeep (NID = 21h): WCap .......................................................................................................292
7.28.1. DigBeep (NID = 21h): OutAmpCap ................................................................................293
7.28.2. DigBeep (NID = 21h): OutAmpLeft ................................................................................293
7.28.3. DigBeep (NID = 21h): PwrState .....................................................................................294
7.28.4. DigBeep (NID = 21h): Gen .............................................................................................295
7.28.5. DigBeep (NID = 21h): Gain ............................................................................................295
7.29. I2C (NID = 22h): WCap ................................................................................................................296
7.29.1. I2C (NID = 22h): Cntrl0 ..................................................................................................297
8. PINOUT AND PACKAGING .................................................................................................. 299
8.0.1. 48QFN Pin Table .............................................................................................................300
8.0.2. 48QFN Package Outline and Package Dimensions ........................................................302
8.1. Standard Reflow Profile Data ........................................................................................................303
9. DISCLAIMER ......................................................................................................................... 304
10. DOCUMENT REVISION HISTORY ..................................................................................... 305
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
8
V 1.1 1/12
92HD92
Datasheet pdf - http://www.DataSheet4U.co.kr/







92HD92 equivalent, schematic
92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
AFG
Power
State
RESET#
D0
De-Asserted
(High)
D1-D2
De-Asserted
(High)
D3
De-Asserted
(High)
D3cold
D4
D5
-
-
-
GPIO0
Enable
Input
Enable
Output
Enable
Converter Stream
Dig En
ID
Keep
Alive
En
Pin Behavior
Disabled Disabled -
- - Hi-Z (internal pull-down enabled)
Disabled
-
Disabled -
-
Enabled
Enabled
0
1-15
-
-
Active - Pin drives 0 (internal
pull-down NA)
Active - Pin drives SPDIF-format, but
data is zeroes (internal pull-down NA)
Active - Pin drives SPDIFOut1 data
(internal pull-down NA)
Disabled -
- - Hi-Z (internal pull-down enabled)
Disabled
Disabled Disabled
Enabled
Enabled
-
-
-
-
Active - Pin drives 0 (internal
pull-down NA)
0
Active - Pin drives 0 (internal
pull-down NA)
1
Active - Pin drives SPDIF-format, but
data is zeroes (internal pull-down NA)
Disabled -
- - Hi-Z (internal pull-down enabled)
Disabled Disabled
Enabled
Disabled
Enabled
-
-
-
- Hi-Z (internal pull-down enabled)
0 Hi-Z (internal pull-down enabled)
1
Active - Pin drives SPDIF-format, but
data is zeroes (internal pull-down NA)
Disabled Disabled -
-
- - Hi-Z (internal pull-down enabled)
- - - - - - Hi-Z (port off)www.DataSheet.net/
----
- - Hi-Z (port off)
Table 5. SPDIF OUT 1 Behavior
2.2. Mono Output
The Mono Out port source selection, power state, and mute characteristics are all independently
controlled by the mono output port controls. EQ does not apply to this path. An internal 2nd order
band-pass filter is provided to restrict the output frequencies when using mono out to drive an exter-
nal amplified sub-woofer.
The following sources are available for the Mono Out pin:
• DAC0 Output: When selected (by using the port connection list), the DAC0 left and right outputs
are summed together.
• DAC1 Output: When selected (by using the port connection list), the DAC1 left and right outputs
are summed together.
• Mixer Output: When selected (by using the port connection list), the mixer left and right outputs
are summed together.
The stereo inputs are scaled by -6dB and then summed to provide an output that is the average of
the two inputs. The full scale output at mono out is designed to be about 0dBV. It is not possible to
adjust to a +3dBV output level.
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
16
V 1.1 1/12
92HD92
Datasheet pdf - http://www.DataSheet4U.co.kr/










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