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PDF ( 数据手册 , 数据表 ) D78CP18

零件编号 D78CP18
描述 UPD78CP18
制造商 NEC
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D78CP18 数据手册, 描述, 功能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78CP18(A)
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD78CP18(A) is a version of the µPD78C18(A) in which the internal mask ROM is replaced by one-time PROM.
The one-time PROM version can be programmed once only by users, and is ideally suited for small-scall of many
differnt products, and rapid development and time-to-market of a new product.
The detailed functions are descrived in the following user's manual. Read this manual before starting design
work.
87AD series µPD78C18 user's manual: IEU-1314
FEATURES
High reliability compared to the µPD78CP18
Compatible with the µPD78C11A(A), 78C12A(A), 78C14(A), 78C18(A)
Internal PROM: 32768 W × 8
• Internal PROM capacity can be changed by software to conform to the µPD78C11A(A), 78C12A(A), 78C14(A),
78C18(A).
PROM programming characteristics: µPD27C256A compatiblewww.DataSheet.net/
Power supply voltage range: 5 V ± 10 %
Supports QTOPmicrocomputer
5
Remark QTOP microcomputer is the generic name of NEC's single-chip microcomputers for which NEC
provides total service including writing, marking, screening, and inspection.
ORDERING INFORMATION
Part Number
µPD78CP18GF(A)-3BE
µPD78CP18GQ(A)-36
Package
64-pin plastic QFP (14 × 20 mm)
64-pin plastic QUIP
Internal ROM
One-time PROM
One-time PROM
QUALITY GRADE
Part Number
µPD78CP18GF(A)-3BE
µPD78CP18GQ(A)-36
Quality Grade
Special
Special
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Document No. IC-3233A
(O. D. No. IC-8702A)
Date Published March 1995 P
Printed in Japan
The information in this document is subject to change without notice.
The mark 5 shows major revised points.
©
11999943
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D78CP18 pdf, 数据表
µPD78CP18(A)
1.2 NON-PORT FUNCTIONS (IN NORMAL OPERATION)
Pin Name
TXD
(Transmit Data)
I/O
Output
Alternate
Function Pin
PC0
Serial data output pin
Function
RXD
(Receive Data)
Input
PC1
Serial data input pin
SCK
(Serial Clock)
Input/output PC2
Serial clock input/output pin. Output when internal clock is used, input
when external clock is used.
INT2
Input
(Interrupt Request)
TI
(Timer Input)
Input
PC3
Edge trigger (falling edge) maskable interrupt input pin
Timer external clock input pin
Zero-cross
Input
AC input zero-cross detection pin
TO
(Timer Output)
Output
PC4
During timer count time, square wave with one internal clock cycle as
one half cycle is output.
CI
(Counter Input)
Input
PC5
Timer/event counter external pulse input pin
CO0 and CO1
(Counter
Output 0, 1)
Output
PC6 and PC7 Square wave output programmable by timer/event counter.
AD7 to AD0
(Address/Data
Bus 7 to 0)
Input/output
AB15 to AB8
(Address Bus
15 to 8)
Output
WR
(Write Strobe)
Output
RD
(Read Strobe)
Output
PD7 to PD0
PF7 to PF0
Multiplexed address/data bus when external memory is used
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Address bus when external memory is used
Strobe signal which is output for write operation of external memory. It
becomes high in any cycle other than the data write machine cycle of
external memory. When RESET signal is either low or in the hardware
STOP mode, this signal becomes high-impedance.
Strobe signal which is output for read operation of external memory. It
becomes high in any cycle other than the data read machine cycle of
external memory. When RESET signal is either low or in the hardware STOP
mode, this signal becomes output high-impedance.
ALE Output
(Address
Latch Enable)
MODE0
MODE1
(Mode)
Input
Input/output
Strobe signal to latch externally the lower address information which is
output to PD7 to PD0 pins to access external memory. When RESET signal
is either low or in the hardware STOP mode, this signal becomes high-
impedance.
Set MODE0 pin to “0” (low level), and MODE1 pin to “1” (high level)Note
NMI
Input
(Non-Maskable
Interrupt)
Non-maskable interrupt input pin of the edge trigger (falling edge)
Note Pull-up. Pull-up resister R is 4 [k] R 0.4 tCYC [k] (tCYC is ns unit).
8
Datasheet pdf - http://www.DataSheet4U.co.kr/







D78CP18 equivalent, schematic
µPD78CP18(A)
3. MEMORY EXTENSION
The µPD78CP18(A) allows external memory extension by means of the MEMORY MAPPING register (MM) or the
MODE0 and MODE1 pins. Also, the internal PROM and internal RAM access areas can be specified by means of bits
MM7, MM6 and MM5 of the MEMORY MAPPING register.
3.1 MODE PINS
The µPD78CP18(A) can be switched between programming mode and normal operation mode according to the
specification of the MODE0 and MODE1 pins.
Table 3-1 shows the modes set by the MODE pins.
Table 3-1. Modes Set By MODE Pins
MODE1
L
L
H
H
MODE2
L
H
L
H
Operating Mode
Setting prohibited
Programming modeNote
Normal operation mode
Setting prohibited
Note See 4. “PROM PROGRAMMING”.
When MODE0 and MODE1 are driven high, a 4 [k] R 0.4 tCYC [k] pull-up resistor should be used (tCYC: ns units).
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16
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