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PDF ( 数据手册 , 数据表 ) NB3N501

零件编号 NB3N501
描述 3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier
制造商 ON Semiconductor
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NB3N501 数据手册, 描述, 功能
NB3N501
3.3V / 5.0V 13 MHz to
160 MHz PLL Clock
Multiplier
Description
The NB3N501 is a clock multiplier that will generate one of nine
selectable output multiples of an input frequency via two 3level
select inputs (S0, S1). It accepts a standard fundamental mode crystal
or an external reference clock signal. PhaseLockedLoop (PLL)
design techniques are used to produce a low jitter, TTL level clock
output up to 160 MHz with a 50% duty cycle. An Output Enable (OE)
pin is provided, and when asserted low, the clock output goes into
tristate (high impedance). The NB3N501 is commonly used in
electronic systems as a cost efficient replacement for crystal
oscillators
Features
Clock Output Frequencies up to 160 MHz
Nine Selectable Multipliers of the Input Frequency
Operating Range: VDD = 3.3 V ±10% or 5.0 V ±5%
Low Jitter Output of 25 ps One Sigma (rms)
Zero ppm Clock Multiplication Error
45% 55% Output Duty Cycle
TTL/CMOS Output with 25 mA TTL Level Drive
Crystal Reference Input Range of 5 27 MHz
Input Clock Frequency Range of 2 50 MHz
OE, Output Enable with TriState Output
8Pin SOIC
Industrial Temperature Range 40°C to +85°C
These are PbFree Devices
VDD
http://onsemi.com
8
1
SOIC8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
3N501
ALYWG
G
1
3N501 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
crystal or
clock
CLX2 CLX1
X1/ICLK
Crystal
Oscillator
X2
Multiplier
Select
S1 S0
÷ P Phase
Detector
Charge
Pump
VCO
÷ M Feedback
GND
Figure 1. NB3N501 Logic Diagram
TTL/
CMOS
Output
OE
CLKOUT
© Semiconductor Components Industries, LLC, 2013
November, 2013 Rev. 2
1
Publication Order Number:
NB3N501/D












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