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PDF ( 数据手册 , 数据表 ) A017CN01-V4

零件编号 A017CN01-V4
描述 COLOR TFT-LCD MODULE
制造商 AUO
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A017CN01-V4 数据手册, 描述, 功能
Do c. Ver s io n:
Total Pages:
Date
:
0.6
56
2007.1.18
Product Specification
1.7COLOR TFT-LCD MODULE
MODEL NAME: A017CN01 V4
www.DataSheet.co.kr
< > Preliminary Specification
< > Final Specification
Note: The content of this
specification is subject to
change.
© 2007 AU Optronics
All Rights Reserved,
Do Not Copy.
Datasheet pdf - http://www.DataSheet4U.net/







A017CN01-V4 pdf, 数据表
Version:
Page:
0.6
7 / 56
3. Electrical characteristics
a. Typical operating conditions (GND = AVss = 0V)
Item
Symbol Min. Typ. Max. Unit
Remark
Power Voltage
Output
H Level
Signal Voltage L Level
Input
H Level
Signal Voltage L Level
VCOM Voltage
VCC
PVDD
PVDD
VOH
VOL
VIH
VIL
VCAC
VCDC
2.7 3.3 3.6 V
3.0 3.3 3.6 V
3.0 3.3 3.6 V
Vcc-0.4 -
VCC
V
GND
- GND+0.4 V
0.7xVCC
GND
5.4
-
-
5.8
VCC
0.3VCC
6.4
V
V
V
0.6 0.8 1.0 V
Digital Power Supply
Analog Power Supply
Charge Pump Power Supply
V
V
DRV output voltage
VDRV
0 - VCC
V
Analog stand by current
Ist
- - 100 uA
DCLK is stopped
Note 1: A build-in power on reset circuit for PVDD and VCC is provided within the integrated LCD driver IC. The
LCD module is in power saving mode in default, and stand-by releasing is required after VCC power on through
serial control. Pleaser refer to the register STB setting for detail.
b. Current characteristics (GND = AVss = 0V)
Parameter Symbol Condition
Input Current
for VCC
IVCC (Pin 27)
VCC=3.3V
Input Current
for AVDD
IAVDD (Pin 25)
AVDD=3.3V
Input Current
for PVDD
IPVDD (Pin 19)
PVDD=3.3V
Output
current
Analog stand
by current
H Level
L Level
IAST
IOH
IOL
AVDD=3.3V
Digital stand
by current
IDST
VCC=3.3V
www.DataSheet.co.kr
Min.
Typ.
-- 2
-- 2.5
-- 8
- 400
- -400
- 50
- --
DRV output
current
IDRV
VCC = 3.0V
DRV = 0.7V
-
-
Max.
4
3
10
-
-
100
100
100
Unit Remark
mA
FDCLK = 24.54MHz
mA (UPS052)
Other registers are
default settings
mA
uA
uA
uA STB = ‘L’ and all
function are
uA shutdown
mA
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PRPER SHALL NOT BE REPRODUCED, COPIED, OR
TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
Datasheet pdf - http://www.DataSheet4U.net/







A017CN01-V4 equivalent, schematic
Version:
Page:
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15 / 56
d. CCIR656 Timing conditions
d - 1. CCIR656 timing specifications
Parameter
DCLK Frequency
Period
Display period
HSYNC Back porch
Front porch
Pulse width
Period
Odd
Even
Odd
Display period
Even
VSYNC Back porch
Odd
Even
Front porch
Odd
Even
Pulse width
Odd
Even
Symbol
1/tDCLK
tH
thdisp
thbp
thfp
thsw
Min.
16
1620
241
4
1
tV Note 1
tvdisp
tvbp
tvfp
tvsw
11
10.5
0
0
1
www.DataSheet.co.kr
Typ.
27
1716
1440
273
4
-
262.5
240
18
17.5
4.5
5
-
Max.
27
1809
304
4
-
Note 1
24
23.5
-
-
-
Unit.
MHz
DCLK
DCLK
DCLK
DCLK
DCLK
tH
tH
tH
tH
DCLK
Note 1: Min. and max. value of VSYNC period are related to Hsync period and Vs back porch.
Note 2: Please keep frame over 50 Hz to get the better display quality.
Remark
Note 2
DCLK
(27MHz)
D[7..0]
Invalid Data
FFh 00h 00h XY Cb0 Y0
(SAV)
Cr0 Y1
Cb
718
Y718
Cr
718
Y719 FFh
00h
00h
XY
720 CCIR valid data
(EAV)
Invalid
Data
d- 2. CCIR656 decoding:
CCIR656 Data input format
FF 00 00 XY signals are involved with HSYNC, VSYNC and Field.
XY encodes following bits:
F = field select
V = indicate vertical blanking
H = 1 if EAV else 0 for SAV
P3-P0 = protection bits
⊕ ⊕ ⊕ ⊕ ⊕P3 = V H, P2 = F H, P1 = F V, P0 = F V H
represents the exclusive-OR function.
It is controlled by “End of Video” (EAV) and “Start of Video” (SAV) timing references.
Horizontal blanking section consists of repeating pattern 80 10 80 10
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