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PDF ( 数据手册 , 数据表 ) 8502A

零件编号 8502A
描述 ISL8502A
制造商 Intersil Corporation
LOGO Intersil Corporation LOGO 


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8502A 数据手册, 描述, 功能
2A Synchronous Buck Regulator with Integrated
MOSFETs
ISL8502A
The ISL8502A is a synchronous buck controller with internal
MOSFETs packaged in a small 4mmx4mm QFN package. The
ISL8502A can support a continuous load of 2A and has a very
wide input voltage range. With the switching MOSFETs
integrated into the IC, the complete regulator footprint can be
very small and provide a much more efficient solution than a
linear regulator.
The ISL8502A is capable of stand-alone operation or it can be
used in a master slave combination for multiple outputs that
are derived from the same input rail. Multiple slave channels
(up to six) can be synchronized. This method minimizes the
EMI and beat frequencies effect with multi-channel operation.
The switching PWM controller drives two internal N-Channel
MOSFETs in a synchronous-rectified buck converter topology.
The synchronous buck converter uses voltage-mode control
with fast transient response. The switching regulator provides
a maximum static regulation tolerance of ±1% over line, load,
and temperature ranges. The output is user-adjustable by
means of external resistors down to 0.6V.
The output is monitored for undervoltage events. The switching
regulator also has overcurrent protection. Thermal shutdown is
integrated. The ISL8502A features a bi-directional Enable pin
that allows the part to pull the enable pin low during fault
detection.
PGOOD delay for ISL8502A has been decreased to 1ms typical
(at 500kHz switching frequency) compared to 250ms (at
500kHz) for ISL8502.
Features
• Up to 2A Continuous Output Current
• Integrated MOSFETs for Small Regulator Footprint
• Adjustable Switching Frequency, 500kHz to 1.2MHz
• Tight Output Voltage Regulation, ±1% Over-temperature
• Wide Input Voltage Range, 5V ±10% or 5.5V to 14V
• Wide Output Voltage Range, from 0.6V
• Simple Single-Loop Voltage-Mode PWM Control Design
• Input Voltage Feed-Forward for Constant Modulator Gain
• Fast PWM Converter Transient Response
• Lossless rDS(ON) High Side and Low Side Overcurrent
Protections
• Undervoltage Detection
• Integrated Thermal Shutdown Protection
• Power-Good Indication
• Adjustable Soft-Start
• Start-Up with Pre-Bias Output
• Pb-free (RoHS Compliant)
Applications
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Point of Load Applications
Graphics Cards - GPU and Memory Supplies
• ASIC Power Supplies
• Embedded Processor and I/O Supplies
• DSP Supplies
POWER GOOD
ENABLE
PGOOD
EN
VIN
+
VIN
5.5V TO 14V
POWER GOOD
ENABLE
SYNCH
M/S
BOOT
VCC
PVCC
SS
ISL8502A
PHASE
VOUT
+
PGND
FS
FB
SGND
COMP
PGOOD
EN
PVCC
VCC
SS
SYNCH
M/S
FS
SGND
VIN
BOOT
ISL8502A
PHASE
PGND
FB
COMP
4.5V TO 5.5VVIN
+
VOUT
+
FIGURE 1. STAND-ALONE REGULATOR: VIN 5.5V TO 14V
FIGURE 2. STAND-ALONE REGULATOR: VIN 4.5V TO 5.5V
October 21, 2011
FN7940.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/







8502A pdf, 数据表
ISL8502A
Typical Performance Curves VIN = 12V, VOUT = 2.5V, IO = 2A, fs = 500kHz, L = 4.7µH, CIN = 20µF,
COUT = 100µF + 22µF, TA = +25° C, unless otherwise noted.
100 100
90 90
80
VOUT = 2.5V
70 VOUT = 1.8V
VOUT = 3.3V
60
50
40
0.0 0.5 1.0 1.5 2.0
OUTPUT LOAD (A)
FIGURE 5. EFFICIENCY vs LOAD (VIN = 5V)
2.5
80
70 VOUT = 5.0V
VOUT = 3.3V
VOUT = 2.5V
60 VOUT = 1.8V
50
40
0.0 0.5 1.0 1.5 2.0
OUTPUT LOAD (A)
FIGURE 6. EFFICIENCY vs LOAD (VIN = 12V)
2.5
0.6026
0.6025
0.6024
0.6023
0.6022
14VIN
0.6021
9VIN
0.6020
5VIN
0.6019
0
1
OUTPUT LOAD (A)
2
FIGURE 7. VOUT REGULATION vs LOAD (VOUT = 0.6V, 500kHz)
1.206
1.205
14VIN
1.204
1.203
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1.202
1.201
9VIN
5VIN
1.200
0
1
OUTPUT LOAD (A)
2
FIGURE 8. VOUT REGULATION vs LOAD (VOUT = 1.2V, 500kHz)
1.520
1.518
1.516
5VIN
1.514
1.512
9VIN
14VIN
1.510
0
1
OUTPUT LOAD (A)
2
FIGURE 9. VOUT REGULATION vs LOAD (VOUT = 1.5V, 500kHz)
1.815
1.815
1.814
5VIN
1.814
1.813
1.813
1.812
1.812
9VIN
14VIN
1.811
1.811
1.810
0
1
OUTPUT LOAD (A)
2
FIGURE 10. VOUT REGULATION vs LOAD (VOUT = 1.8V, 500kHz)
8 FN7940.0
October 21, 2011
Datasheet pdf - http://www.DataSheet4U.net/







8502A equivalent, schematic
ISL8502A
Increasing the value of inductance reduces the ripple current and
voltage. However, the large inductance values reduce the
converter response time to a load transient.
One of the parameters limiting converter response to a load
transient is the time required to change the inductor current.
Given a sufficiently fast control loop design, the ISL8502A
provides either 0% or 100% duty cycle in response to a load
transient. The response time is the time required to slew the
inductor current from an initial current value to the transient
current level. During this interval, the difference between the
inductor current and the transient current level must be
supplied by the output capacitor. Minimizing the response time
can minimize the output capacitance required.
The response time to a transient is different for the application of
load and the removal of load. Equation 9 gives the approximate
response time interval for application and removal of a transient
load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
(EQ. 9)
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst-case response
time can be either at the application or removal of load. Be sure
to check both of these equations at the minimum and maximum
output levels for the worst-case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors for
high-frequency decoupling, and bulk capacitors to supply the
current needed each time the upper MOSFET turns on. Place the
small ceramic capacitors physically close to the MOSFETs and
between the drain of the upper MOSFET and the source of the
lower MOSFET.
The important parameters for bulk input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and largest RMS current required by the
circuit. Their voltage rating should be at least 1.25x greater than
the maximum input voltage, while a voltage rating of 1.5x is a
conservative guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately one-half the DC load current.
The maximum RMS current through the input capacitors can be
closely approximated using Equation 10:
V-----O----U---T-
VIN
×
IO
UTM
A
2
X
×
1
V--V--O--I-U-N--T-⎠⎞
+
--1----
12
×
-V----I-N-----–-----V----O----U---T-
L × fOSC
×
-V--V--O--I--UN---T-⎠⎟⎞
2
(EQ. 10)
For a through-hole design, several electrolytic capacitors may be
needed. For surface mount designs, solid tantalum capacitors
can be used, but caution must be exercised with regard to the
capacitor surge current rating. These capacitors must be capable
of handling the surge current at power-up. Some capacitor series
available from reputable manufacturers are surge current tested.
Feedback Compensation
Figure 36 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage (VOUT)
is regulated to the reference voltage level. The error amplifier
output (VE/A) is compared with the oscillator (OSC) triangular
wave to provide a pulse-width modulated (PWM) wave with an
amplitude of VIN at the PHASE node. The PWM wave is smoothed
by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC gain
and the output filter (LO and CO), with a double pole break
frequency at FLC and a zero at FESR. The DC gain of the
modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage, DVOSC. The ISL8502A
incorporates a feed-forward loop that accounts for changes in the
input voltage. This configuration maintains a constant modulator
gain.
OSC
PWM
COMPARATOR
Δ VOSC
-
+
DRIVER
DRIVER
VIN
LO
PHASE CO
VOUT
ESR
(PARASITIC)
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
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DETAILED COMPENSATION COMPONENTS
C1
C2 R2
ZFB VOUT
ZIN
C3 R3
COMP
R1
FB
-
+
ISL8502A
REFERENCE
R4
VOUT
=
0.6
×
1
+
RR-----14- ⎠⎟⎞
FIGURE 36. VOLTAGE-MODE BUCK CONVERTER COMPENSATION
DESIGN AND OUTPUT VOLTAGE SELECTION
Modulator Break Frequency Equations
fLC=
---------------------1---------------------
2π x LO x CO
fESR=
---------------------1----------------------
2π x ESR x CO
(EQ. 11)
The compensation network consists of the error amplifier
(internal to the ISL8502A) and the impedance networks, ZIN and
ZFB. The goal of the compensation network is to provide a closed
loop transfer function with the highest 0dB crossing frequency
16
FN7940.0
October 21, 2011
Datasheet pdf - http://www.DataSheet4U.net/










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