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PDF ( 数据手册 , 数据表 ) ADP1046

零件编号 ADP1046
描述 Digital Controller
制造商 Analog Devices
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ADP1046 数据手册, 描述, 功能
Data Sheet
Digital Controller for Isolated
Power Supply Applications
ADP1046
FEATURES
GENERAL DESCRIPTION
Integrates all typical PWM controller functions
7 PWM control signals
Digital control loop
Integrated programmable loop filters
Programmable voltage line feedforward
Dedicated soft start filter
Programmable dead time for improved efficiency
Remote and local voltage sense
Primary and secondary side current sense
Synchronous rectifier control
Current sharing
OrFET control
I2C interface
Extensive fault detection and protection
Extensive programming and telemetry
Fast digital calibration
User accessible EEPROM
APPLICATIONS
AC-to-DC power supplies
Isolated dc-to-dc power supplies
Redundant power supply systems
Server, storage, network, and communications
infrastructure
The ADP1046 is a flexible, digital secondary side controller
designed for ac-to-dc and isolated dc-to-dc secondary side
applications. The ADP1046 is pin-compatible with the
ADP1043A and offers several enhancements and new features,
including voltage feedforward, improved loop response, and
programmable dead time control to maximize efficiency.
The ADP1046 is optimized for minimal component count,
maximum flexibility, and minimum design time. Features
include local and remote voltage sense, primary and secondary
side current sense, digital pulse-width modulation (PWM)
generation, current sharing, and redundant OrFET control. The
control loop digital filter and compensation terms are integrated
and can be programmed over the I2C interface. Programmable
protection features include overcurrent protection (OCP), over-
voltage protection (OVP), undervoltage lockout (UVLO), and
overtemperature protection (OTP).
The built-in EEPROM provides extensive programming of the
integrated loop filter, PWM signal timing, inrush current, and
soft start timing and sequencing. Reliability is improved through
a built-in checksum and programmable protection circuits.
www.DataSheet.co.kr A comprehensive GUI is provided for easy design of loop
filter characteristics and programming of the safety features.
The industry-standard I2C bus provides access to the many
monitoring and system test functions.
The ADP1046 is available in a 32-lead LFCSP and operates
from a single 3.3 V supply.
TYPICAL APPLICATION CIRCUIT
DC
INPUT
LOAD
DRIVER
iCoupler
DRIVER
DRIVER
SR1 SR2
CS1
ACSNS
CS2– CS2+ PGND
VS1 GATE VS2
VS3+
OUTA
OUTB
OUTC
OUTD
ADP1046
OUTAUX
RES ADD RTD VCORE FLAGIN PSON PGOOD2 PGOOD1 SDA SCL
VS3–
SHAREo
SHAREi
VDD DGND AGND
VDD
MICROCONTROLLER
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.net/







ADP1046 pdf, 数据表
ADP1046
Parameter
Measurement Accuracy
Temperature Readings
According to Internal
Linearization Scheme
OTP
Threshold Accuracy
Comparator Speed
OTP Threshold Hysteresis
PGOOD1, PGOOD2, SHAREo PINS
(OPEN DRAIN)
Output Low Voltage
PSON, FLAGIN, SHAREi PINS
(DIGITAL INPUTS)
Input Low Voltage
Input High Voltage
FLAGIN Propagation Delay
Leakage Current
GATE PIN
Output Low Voltage
Output High Voltage
SDA/SCL PINS
Input Low Voltage
Input High Voltage
Output Low Voltage
Leakage Current
SERIAL BUS TIMING
Clock Operating Frequency
Bus-Free Time
Start Hold Time
Start Setup Time
Stop Setup Time
SDA Setup Time
SDA Hold Time
SCL Low Timeout
SCL Low Period
SCL High Period
Clock Low Extend Time
SCL, SDA Fall Time
SCL, SDA Rise Time
Symbol
Test Conditions/Comments
Factory trimmed at 1 V
0 mV to 160 mV
0% to 100% of usable input voltage range
RTD source set to 46 μA (Register 0x11 set to
0xE6); NTC R0 = 100 kΩ, 1%, beta = 4250, 1%;
REXT = 16.5 kΩ, 1%
25°C to 100°C
100°C to 125°C
Min
−0.5
−8
−3.0
−42
T = 85°C with 100 kΩ||16.5 kΩ
T = 100°C with 100 kΩ||16.5 kΩ
−0.9
−14.4
−0.5
−8
Typ
10.5
16
VOL
VIL
VIH VDD − 0.4
Does not include debounce time (Register
200
0x0A[3] = 1); flag action set to disable PSU
www.DataSheet.co.kr
VOL
VOH
VDD = 3.3 V
VIL
VIH
VOL
VDD − 0.4
VDD − 0.4
tBUF
tHD;STA
tSU;STA
tSU;STO
tSU;DAT
tHD;DAT
tTIMEOUT
tLOW
tHIGH
tLO;SEXT
tF
tR
See Figure 3
Between stop and start conditions
Hold time after (repeated) start condition;
after this period, the first clock is generated
Repeated start condition setup time
For readback
For write
10
1.3
0.6
0.6
0.6
100
125
300
25
1.3
0.6
20
20
100
Data Sheet
Max Unit
+0.5 % FSR
+8 mV
+3.0 % FSR
+42 mV
7
5
+0.25
+4
+1.1
+17.6
°C
°C
% FSR
mV
% FSR
mV
ms
mV
0.4 V
0.4 V
V
ns
1.0 μA
0.4 V
V
0.4 V
V
0.4 V
1.0 μA
400 kHz
μs
μs
μs
μs
ns
ns
ns
35 ms
μs
μs
25 ms
300 ns
300 ns
Rev. 0 | Page 8 of 96
Datasheet pdf - http://www.DataSheet4U.net/







ADP1046 equivalent, schematic
ADP1046
Data Sheet
VOLTAGE SENSE AND CONTROL LOOP
Multiple voltage sense inputs on the ADP1046 are used for the
monitoring, control, and protection of the power supply output.
This information is available through the I2C interface. All voltage
sense points can be calibrated digitally to minimize errors due to
external components. This calibration can be performed in the
production environment, and the settings can be stored in the
EEPROM of the ADP1046 (see the Power Supply Calibration
and Trim section for more information).
For voltage monitoring, the VS1, VS2, and VS3 voltage value
registers (Register 0x15, Register 0x16, and Register 0x17,
respectively) are updated every 10 ms. The ADP1046 stores every
ADC sample for 10 ms and then outputs the average value at the
end of the 10 ms period. Therefore, if these registers are read at
least every 10 ms, a true average value is read.
The ADP1046 uses two separate sensing points: VS1 and VS3±,
depending on the condition of the OrFET. When the OrFET is
turned off, the control loop is regulated via VS1; when the OrFET
is turned on, the control loop is regulated via the differential
sensing on VS3±. This sensing mechanism effectively performs
a local and remote voltage sense.
The control loop of the ADP1046 features a patented multipath
architecture. The output voltage is converted simultaneously by
two ADCs: a high accuracy ADC and a high speed ADC. The
complete signal is reconstructed and processed in the digital
filter to provide a high performance, cost competitive solution.
12V 12V
12V
LOAD
PGND
11k
11k
1V 1V
1k1k
VS1 VS2
VS1 ADC VS2 ADC VS3 ADC
12 BITS 12 BITS
12 BITS
VS3
HF
ADC
DIGITAL
FILTER
VS3+
VS3–
11k
1V
1k
Figure 16. Voltage Sense Configuration
ADCs
Two kinds of Σ-Δ ADCs are used in the feedback loop of the
ADP1046: a low frequency (LF) ADC that runs at 1.56 MHz
and a high frequency (HF) ADC that runs at 25 MHz.
Σ-Δ ADCs have a resolution of one bit and operate differently
from traditional flash ADCs. The equivalent resolution obtain-
able depends on how long the output bit stream of the Σ-Δ is
sampled.
Σ-Δ ADCs also differ from Nyquist rate ADCs in that the quan-
tization noise is not uniform across the frequency spectrum. At
lower frequencies, the noise is lower, and at higher frequencies,
the noise is higher (see Figure 17).
NYQUIST ADC
NOISE
Σ-ADC
NOISE
FREQUENCY
Figure 17. Noise Performance for Nyquist Rate and Σ-Δ ADCs
The low frequency ADC runs at approximately 1.56 MHz. For a
specified bandwidth, the equivalent resolution can be calculated
as follows:
ln(1.56 MHz/BW)/ln2 = N bits
For example, at a bandwidth of 95 Hz, the equivalent
resolution/noise is
ln(1.5 MHz/95)/ln2 = 14 bits
At a bandwidth of 1.5 kHz, the equivalent resolution/noise is
ln(1.56 MHz/1.5 kHz)/ln2 = 10 bits
The high frequency ADC has a clock of 25 MHz. It is comb
filtered and outputs at the switching frequency (fSW) into the
digitalwww.DataSheet.co.kr filter. The equivalent resolution at some sample
frequencies is listed in Table 5.
Table 5. Equivalent Resolutions for High Frequency ADC
at Various Switching Frequencies
fSW (kHz)
High Frequency ADC Resolution
48.8 9 bits
97.7 8 bits
195.3
7 bits
390.6
6 bits
The HF ADC has a range of ±30 mV. Using a base switching
frequency (fSW) of 100 kHz (8-bit HF ADC resolution), when fSW
increases to 200 kHz (7-bit HF ADC resolution), the quantization
noise is 0.9375 mV (1 LSB). Increasing fSW to 400 kHz increases the
quantization noise to 3.75 mV (1 LSB = 2 × 30 mV/26 = 0.9375 mV).
VS1 OPERATION (VS1)
VS1 is used for the monitoring and protection of the power supply
voltage at the output of the LC stage, upstream of the OrFET. The
VS1 sense point on the power rail needs an external resistor
divider to bring the nominal input voltage to 1 V at the VS1 pin
(see Figure 16). The resistor divider is necessary because the VS1
ADC input range is 0 V to 1.6 V (12-bit reading). This divided-
down signal is internally fed into a low speed Σ-Δ ADC. The output
of the VS1 ADC goes to the digital filter and is also updated in
Register 0x15 every 10 ms. The VS1 signal is referenced to PGND.
When the OrFET is turned off, the power supply is regulated
from the VS1 sense point instead of the VS3± sense point.
Rev. 0 | Page 16 of 96
Datasheet pdf - http://www.DataSheet4U.net/










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