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PDF ( 数据手册 , 数据表 ) W6810

零件编号 W6810
描述 SINGLE CHANNEL VOICECODEC
制造商 Nuvoton Technology
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W6810 数据手册, 描述, 功能
W6810 SINGLE CHANNEL VOICECODEC
1. GENERAL DESCRIPTION
The W6810 is a general-purpose single channel PCM CODEC with pin-selectable -Law or A-Law companding.
The device is compliant with the ITU G.712 specification. It operates off of a single +5V power supply and is
available in 20-pin SOG, SSOP, and TSSOP package options.. Functions performed include digitization and
reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are
compliant with ITU G.712 specification. W6810 performance is specified over the industrial temperature range of
40C to +85C.
The W6810 includes an on-chip precision voltage reference and an additional power amplifier, capable of driving
300loads differentially up to a level of 6.3V peak-to-peak. The analog section is fully differential, reducing noise
and improving the power supply rejection ratio. The data transfer protocol supports both long-frame and short-
frame synchronous communications for PCM applications, and IDL and GCI communications for ISDN
applications. W6810 accepts seven master clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-
scaler automatically determines the division ratio for the required internal clock.
For fast evaluation and prototyping purposes, the W6810DK development kit is available.
2. FEATURES
Single +5V power supply
Typical power dissipation of 25 mW, power-
down mode of 0.5 W
Fully-differential analog circuit design
On-chip precision reference of 1.575 V for a 0
dBm TLP at 600 (775mVRMS)
Push-pull power amplifiers with external gain
adjustment with 300 load capability
Seven master clock rates of 256 kHz to 4.096
MHz
Pin-selectable -Law and A-Law companding
(compliant with ITU G.711)
CODEC A/D and D/A filtering compliant with
ITU G.712
Industrial temperature range (40C to +85C)
Three packages: 20-pin SOG, SSOP, and
TSSOP
Pb-Free / RoHS package options available
ApplIcations
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Digital Telephone Systems
Central Office Equipment (Gateways, Switches,
Routers)
PBX Systems (Gateways, Switches)
PABX/SOHO Systems
Local Loop card
SOHO Routers
VoIP Terminals
Enterprise Phones
ISDN Terminals
Analog line cards
Digital Voice Recorder
Revision A16
-1-
January 2011
Datasheet pdf - http://www.DataSheet4U.net/







W6810 pdf, 数据表
W6810 SINGLE CHANNEL VOICECODEC
7. FUNCTIONAL DESCRIPTION
W6810 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC complies with the
specifications of the ITU-T G.712 recommendation. The CODEC also includes a complete -Law and A-Law
compander. The -Law and A-Law companders are designed to comply with the specifications of the ITU-T
G.711 recommendation.
The block diagram in section 3 shows the main components of the W6810. The chip consists of a PCM interface,
which can process long and short frame sync formats, as well as GCI and IDL formats. The pre-scaler of the chip
provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync
frequency. The power conditioning block provides the internal power supply for the digital and the analog
section, while the voltage reference block provides a precision analog ground voltage for the analog signal
processing. The main CODEC block diagram is shown in section 3.
8
/A--
CCoonntrtol
ro
l
D/A
Converter
w
8 A/D
Converter
C/oA-nCto/Ant-rol
r
Receive Path
VAAG + -
G -+
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fC= 3400Hz
SSHmmooootthing
hnziFilter
g1
Smoothing
hniFilter
g2
+
-
Transmit Path
ffCC== 220000Hz
HHiHgighhPass
PzaFsilter
se
fC== 3400Hz
AAnn3Htt--4AA0lli0iaassing
i zFinlter
g
Ant-Aliasing
Filter
Figure 7.1 The W6810 Signal Path
++
-
PAO+
PAO-
PAI
RO -
AO
AI+
AI -
Revision A16
-8-
January 2011
Datasheet pdf - http://www.DataSheet4U.net/







W6810 equivalent, schematic
W6810 SINGLE CHANNEL VOICECODEC
SYMBOL
DESCRIPTION
MIN
1/TFS
FST, FSR Frequency
---
1/TBCK BCLKT, BCLKR Frequency
64
TBCKH
BCLKT, BCLKR High Pulse Width
50
TBCKL
TFTRH
BCLKT, BCLKR Low Pulse Width
BCLKT 1 Falling Edge to FST Rising Edge Hold Time
50
20
TFTRS
FST Rising Edge to BCLKT 0 Falling edge Setup Time
80
TFTFH
BCLKT 0 Falling Edge to FST Falling Edge Hold Time
50
TFTFS
FST Falling Edge to BCLKT 1 Falling Edge Setup Time
50
TBDTD
THID
TFRRH
BCLKT Rising Edge to Valid PCMT Delay Time
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Delay Time from BCLKT 8 Falling Edge to PCMT Output
High Impedance
BCLKR 1 Falling Edge to FSR Rising Edge Hold Time
10
10
20
TFRRS
FSR Rising Edge to BCLKR 0 Falling edge Setup Time
80
TFRFH
BCLKR 0 Falling Edge to FSR Falling Edge Hold Time
50
TFRFS
FSR Falling Edge to BCLKR 1 Falling Edge Setup Time
50
TDRS
Valid PCMR to BCLKR Falling Edge Setup Time
0
TDRH
PCMR Hold Time from BCLKR Falling Edge
50
Table 8.2 Short Frame Sync PCM Timing Parameters
TYP MAX UNIT
8 --- kHz
--- 4096 kHz
--- ---
ns
--- ---
ns
--- ---
ns
--- ---
ns
--- ---
ns
--- ---
ns
--- 60
ns
--- 60
ns
--- ---
--- ---
--- ---
--- ---
--- ---
--- ---
ns
ns
ns
ns
ns
ns
Revision A16
- 16 -
January 2011
Datasheet pdf - http://www.DataSheet4U.net/










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