DataSheet8.cn


PDF ( 数据手册 , 数据表 ) W65C134S

零件编号 W65C134S
描述 Microcomputer
制造商 The Western Design Center
LOGO The Western Design Center LOGO 


1 Page

No Preview Available !

W65C134S 数据手册, 描述, 功能
The Western Design Center, Inc.
May 2003
W65C134S Data Sheet
W65C134S
DATA SHEET
www.DataSheet.co.kr
© The Western Design Center, Inc., 2003. All rights reserved
WDC
Datasheet pdf - http://www.DataSheet4U.net/







W65C134S pdf, 数据表
The Western Design Center, Inc.
W65C134S Data Sheet
7 6 5 4 3 2 1 0 TCR1x($000A)
Monitor Watch Dog Timer M
Load Enable
0 to 1 transition loads the Timer
M from the Timer M latches
PHI2 System Timing Clock Select
0 = PHI2 clock source is CLK (Clock)
1 = PHI2 clock source is FCLK (Fast Clock)
FCLK Start and Stop Control
0 = Stop FCLK
1 = Start FCLK
Timer A Enable
0 = TA clock disabled (counter stopped)
1 = TA clock enabled. This bit should be set to a 1 for UART
operation
Timer A Clock Select
0 = Timer A counts PHI2 clock pulses
1 = Timer A counts TIN negative pulses. When ACSR5=1, Timer A and RXD are
www.DataSheet.co.kr
used for the UART and this bit should be cleared to "0".
Timer A Output Enable
0 = Timer A output disabled
1 = Timer A TOUT enabled. When ACSR0=1, Timer A and TXD are used for the UART.
Timer A Interrupt Enable
0 = Timer A Interrupt Disabled.
1 = Timer A Interrupt Enabled.
Timer A Edge Interrupt Flag
0 = Timer A Edge Interrupt has not occurred. This bit cannot be set when UART is in operation.
1 = Timer A edge Interrupt has occurred. This interrupt vector is located at the Asynchronous Transmitter vector
location. This bit is cleared to a "0" by writing a "1" to it. Writing a "0" to this bit has no affect.
Figure 1-3 Timer Control Register One (TCR1x) ($000A)
The Western Design Center, Inc.
W65C134S Data Sheet
8
Datasheet pdf - http://www.DataSheet4U.net/







W65C134S equivalent, schematic
The Western Design Center, Inc.
ACSR3:
ACSR4:
ACSR5:
ACSR6:
ACSR7:
W65C134S Data Sheet
When writing to the Transmitter in seven bit mode, bit 7 is discarded. When reading
from the receive data register during seven bit mode, bit 7 is always zero. When
ACSR2=1, the Transmitter and Receiver send and receive 8-bit data. The Transmitter
sends 11 bits of information (one start, 8 data, one parity and one stop or two stop bits).
The Receiver receives 10 or 11 bits of information (one start, 8 data, one stop or one
parity and one stop bit). A RESET clears ACSR2.
Parity Enable. When ACSR3=0, parity is disabled. A RESET clears ACSR3. When
ACSR3=1, parity is enabled for both the Transmitter and Receiver.
Odd or Even Parity. When ACSR4=0 and parity is enabled, then Odd parity is
generated where the number of ones is the data register plus parity bit equal an odd
number of "1's". When ACSR4=1 and parity is enabled, then Even parity is generated
where the number of ones in the data register plus parity bit equal an even number of
"1's". ACSR4 is cleared by Reset.
Receiver Enable. The Asynchronous Receiver is enabled when ACSR5=1. A
RESET clears ACSR5. When ACSR5=1 the Receiver is enabled and Receiver
Interrupts occurs anytime the contents of the Receiver shift register contents are
transferred to the Receiver Data Register. The Receiver Interrupt is cleared when the
Receive Data Register is read ($0023). The Receive data, RxD, is enabled on P60
when ACSR5=1. When ACSR5=0, all Receiver operation is disabled and all Receive
logic is cleared, the Receiver data register bits 0-6 are not affected and bit 7 is cleared.
Software Semaphore. ACSR6 may be used for communications among routines
which access the UART. This bit has no effect on the UART operation and is cleared
upon a RESET. This signal can be thought of as a manually set “busy” signal.
Receiver Error Flag. The Receiver logic detects three possible error conditions and
www.DataSheet.co.kr
sets ACSR7: parity, framing or over-run. A parity error occurs when the parity bit
received does not match the parity generated on the receive data. A framing error
occurs when the stop bit time finds a "0" instead of a "1". An over-run occurs when
the last data in the Receiver Data Register has not been read and new data is
transferred from the Receive Shift Register. ACSR7 is cleared by a RESET or upon
writing a "1" to ACSR7. Writing a "0" to ACSR7 has no effect on ACSR7.
The Western Design Center, Inc.
W65C134S Data Sheet
16
Datasheet pdf - http://www.DataSheet4U.net/










页数 30 页
下载[ W65C134S.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
W65C134SMicrocomputerThe Western Design Center
The Western Design Center

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap