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PDF ( 数据手册 , 数据表 ) ADV3205

零件编号 ADV3205
描述 16 X 16 Buffered Analog Crosspoint Switch
制造商 Analog Devices
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ADV3205 数据手册, 描述, 功能
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Data Sheet
60 MHz, G = +2, 16 × 16
Buffered Analog Crosspoint Switch
ADV3205
FEATURES
16 × 16 high speed nonblocking switch array
Serial or parallel programming of switch array
Serial data out allows daisy-chaining control of multiple
16 × 16 devices to create larger switch arrays
Complete solution
Buffered inputs
16 output amplifiers
Operates on ±5 V supplies
Low supply current of 50 mA
Excellent video performance, VS = ±5 V
−3 dB bandwidth: 60 MHz
0.1 dB gain flatness: 10 MHz
0.1% differential gain error (RL = 1 kΩ)
0.1° differential phase error (RL = 1 kΩ)
Low all hostile crosstalk: −67 dB at 5 MHz
Output disable allows connection of multiple devices
without loading the output bus
RESET pin allows disabling of all outputs
Power-on reset capability with capacitor to ground
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
CCTV surveillance
Video routers (NTSC, PAL, S-Video, SECAM)
Video conferencing
CLK
DATA IN
UPDATE
CE
RESET
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
A0
A1
A2
A3
DATA
OUT
80
PARALLEL LATCH
80
DECODE
16 × 5:16 DECODERS
SET
INDIVIDUAL
OR RESET
ALL OUTPUTS
TO “OFF”
16
ADV3205
OUTPUT
256 BUFFER
G = +2
16 INPUTS
SWITCH
MATRIX
16
OUTPUTS
Figure 1.
GENERAL DESCRIPTION
The ADV3205 is a fully buffered crosspoint switch matrix that
operates on ±5 V, making it ideal for video applications. It offers
a −3 dB signal bandwidth of 60 MHz and channel switch times of
less than 60 ns with 0.1% settling. The ADV3205 has excellent
crosstalk performance, and ground/power pins surround all inputs
and outputs to provide extra shielding required for the most
demanding applications. The differential gain and differential
phase of better than 0.1% and 0.1°, respectively, along with 0.1 dB
flatness out to 10 MHz, make the ADV3205 an excellent choice
for many video applications.
The ADV3205 includes 16 independent output buffers that can
be placed into a disabled state for paralleling crosspoint outputs.
The ADV3205 has a gain of +2 and operates on voltage supplies
of ±5 V while consuming only 34 mA of current. Channel
switching is performed via a serial digital control (which can
accommodate daisy-chaining of several devices) or via a parallel
control, allowing updating of an individual output without
reprogramming the entire array.
The ADV3205 is packaged in a 100-lead LQFP and is available
over the commercial temperature range of 0°C to 70°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
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ADV3205 pdf, 数据表
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ADV3205
Pin Number
80
81
82
83
84
85 to 93
94
95
96
97
98
99
100
Data Sheet
Mnemonic
D0
A3
A2
A1
A0
NC
SER/PAR
UPDATE
DATA IN
CLK
DATA OUT
CE
RESET
Description
Parallel Data Input, TTL Compatible (Input Select LSB).
Parallel Data Input, TTL Compatible (Output Select MSB).
Parallel Data Input, TTL Compatible (Output Select).
Parallel Data Input, TTL Compatible (Output Select).
Parallel Data Input, TTL Compatible (Output Select LSB).
No Connect. Do not connect to this pin.
Selects Serial Data Mode, Low or Parallel Data Mode, High.
Enable (Transparent) Low. Allows serial register to connect directly to switch matrix.
Data latched when high.
Serial Data Input, TTL Compatible.
Clock, TTL Compatible. Falling edge triggered.
Serial Data Out, TTL Compatible.
Chip Enable, Enable Low. Must be low to clock in and latch data.
Disable Outputs, Active Low.
Rev. 0 | Page 8 of 20
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ADV3205 equivalent, schematic
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ADV3205
POWER-ON RESET
When powering up the ADV3205, it is usually desirable to have
the outputs start up in the disabled state. The RESET pin, when
taken low, causes all outputs to be in the disabled state. However,
the RESET signal does not reset all registers in the ADV3205.
This is important when operating in parallel programming mode.
Refer to the Parallel Programming section for information
about programming internal registers after power-up. Serial
programming programs the entire matrix each time; therefore,
no special considerations apply.
Because the data in the shift register is random after power-up,
do not use it to program the matrix or the matrix can enter
unknown states. To prevent this, do not apply logic low signals
to both CE and UPDATE initially after power-up. First, load the
shift register with the desired data, and then take UPDATE low
to program the device.
The RESET pin has a 20 kΩ pull-up resistor to DVCC that can be
used to create a simple power-up reset circuit. A capacitor from
RESET to ground holds RESET low for some time while the rest
of the device stabilizes. The low condition causes all outputs to
be disabled. The capacitor then charges through the pull-up resistor
to the high state, thus allowing full programming capability of
the device.
MANAGING VIDEO SIGNALS
Video signals often use controlled impedance transmission lines
that are terminated in their characteristic impedance. Although this
is not always the case, there are some considerations when using
the ADV3205 to route video signals with controlled impedance
transmission lines. Figure 29 shows a schematic of an input
and output treatment of a typical video channel.
75
VIDEO
SOURCE
+5V
TYPICAL
INPUT ADV3205
75G = 2
TYPICAL
OUTPUT
75
75
TRANSMISSION
LINE
75
–5V
Figure 29. Video Signal Circuit
Video signals most often use 75 Ω transmission lines that need
to be terminated with this value of resistance at each end. When
such a source is delivered to one of the ADV3205 inputs, the
high input impedance does not properly terminate these signals.
Therefore, terminate the line with a 75 Ω shunt resistor to
ground. Because video signals are limited in their peak-to-peak
amplitude (typically no more than 1.5 V p-p), there is no need
to attenuate video signals before they pass through the ADV3205.
Data Sheet
The ADV3205 outputs are low impedance and do not properly
terminate the source end of a 75 Ω transmission line. In these
cases, insert a series 75 Ω resistor at an output that drives a video
signal. Then terminate the 75 Ω transmission line with 75 Ω at
its far end. This overall termination scheme divides the amplitude
of the ADV3205 output by two. An overall unity-gain channel is
produced because of the channel gain-of-two of the ADV3205.
CREATING LARGER CROSSPOINT ARRAYS
The ADV3205 is a high density building block for creating
crosspoint arrays of dimensions larger than 16 × 16. Various
features, such as output disable and chip enable, are useful for
creating larger arrays.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required. The
16 × 16 architecture of the ADV3205 contains 256 points, which is
a factor of 64 greater than a 4 × 1 crosspoint (or multiplexer). The
printed circuit board (PCB) area, power consumption, and design
effort savings are readily apparent when compared to using
these smaller devices.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the
availability of that input to be a source for any other outputs.
Some nonblocking crosspoint architectures require more than this
minimum as previously calculated. In addition, there are blocking
architectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statistical
basis that is determined when designing the overall system.
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wire-OR
the outputs together in the vertical direction. The meaning of
horizontal and vertical can best be understood by looking at a
diagram. Figure 30 illustrates this concept for a 32 × 32 crosspoint
array that uses four ADV3205 devices. Note that the 75 Ω source
terminations are not shown on the outputs, but they are required
when driving the 75 Ω transmission lines.
16
IN00 TO IN15
ADV3205
16
16 ADV3205
75
8
16
IN16 TO IN31
ADV3205
16
16
16 ADV3205
75
16
16
Figure 30. 32 × 32 Crosspoint Array Using Four ADV3205 Devices
Rev. 0 | Page 16 of 20
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