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PDF ( 数据手册 , 数据表 ) K30P104M100SF2

零件编号 K30P104M100SF2
描述 K30 Sub-Family
制造商 Freescale Semiconductor
LOGO Freescale Semiconductor LOGO 


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K30P104M100SF2 数据手册, 描述, 功能
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Freescale Semiconductor
Data Sheet: Product Preview
Document Number: K30P104M100SF2
Rev. 1, 11/2010
K30 Sub-Family Data Sheet
Supports the following:
MK30N512VLL100, MK30N512VML100
Features
Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Memories and memory interfaces
– Up to 512 KB program flash memory on non-
FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
Clocks
– 1 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
System peripherals
– 10 low-power modes to provide power optimization
based on application requirements
– Memory protection unit with multi-master
protection
– 16-channel DMA controller, supporting up to 64
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– Hardware random-number generator
– 128-bit unique identification (ID) number per chip
K30P104M100SF2
Human-machine interface
– Segment LCD controller supporting up to 40
frontplanes and 8 backplanes, or 44 frontplanes and
4 backplanes
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
Analog modules
– 16-bit SAR ADC with PGA (x64)
– 12-bit DAC
– Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
– Voltage reference
Timers
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timers
– Two-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
Communication interfaces
– Controller Area Network (CAN) module
– SPI modules
– I2C modules
– UART modules
– Secure Digital host controller (SDHC)
– I2S
This document contains information on a product under development. Freescale
reserves the right to change or discontinue this product without notice.
© 2010–2010 Freescale Semiconductor, Inc.
Preliminary
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K30P104M100SF2 pdf, 数据表
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Terminology and guidelines
3.6 Relationship between ratings and operating requirements
Operating or handling rating (min.)
Operating requirement (min.)
Operating requirement (max.)
Operating or handling rating (max.)
Fatal
range
- Probable permanent failure
Limited
operating
range
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Normal
operating
range
- No permanent failure
- Correct operation
Limited
operating
range
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Fatal
range
- Probable permanent failure
Handling range
- No permanent failure
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Min.
Digital I/O weak
pullup/pulldown
current
10
Typ.
70
Max.
130
Unit
µA
K30 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
8
Preliminary
Freescale Semiconductor, Inc.
Datasheet pdf - http://www.DataSheet4U.net/







K30P104M100SF2 equivalent, schematic
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General
7. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks
disabled.
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks disabled except FTFL
• LVD disabled
• No GPIOs toggled
• Code execution from flash
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks enabled but peripherals are not in active operation
• LVD disabled
• No GPIOs toggled
• Code execution from flash
K30 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
16
Preliminary
Freescale Semiconductor, Inc.
Datasheet pdf - http://www.DataSheet4U.net/










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