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PDF ( 数据手册 , 数据表 ) LE25LB1282TT

零件编号 LE25LB1282TT
描述 Serial SPI EEPROM
制造商 Sanyo Semicon Device
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LE25LB1282TT 数据手册, 描述, 功能
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Ordering number : ENA1311C
LE25LB1282TT
Serial SPI EEPROM
(SPI Bus)(128Kbit)
Overview
The LE25LB1282TT is a 128Kbit EEPROM that supports serial peripheral interface (SPI). It realizes high speed operation
and high level reliability by incorporating SANYO’s high performance CMOS EEPROM technology. The interface is
compatible with SPI bus protocol, therefore, it is best suited for applications that require small-scale rewritable nonvolatile
parameter memory. Moreover, the LE25LB1282TT has a 64 bytes page rewrite function that provides rapid data rewriting.
Features
Capacity
Single supply voltage
Serial interface
Operating clock frequency
Low current dissipation
Page write function
Rewrite time
Number of rewrite times
Data retention period
High reliability
: 128Kbits (16K×8bits)
: 1.8V to 3.6V
: SPI Mode0, Mode3 supported
: 5MHz (2.5V to 3.6V), 3MHz (1.8V to 3.6V)
: Standby
: 3μA (max.)
: Active (Read) : 1mA (max.)
: Active (Rewrite) : 3mA (max.)
: 64bytes
: 10ms
: 106 times
: 20years
: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325)
Incorporates a feature to prohibit write operations under low voltage conditions.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
70611 SY/10511 SY/40809 SY/31809 SY JK/20080822-S00007 No.NA1311-1/14
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LE25LB1282TT pdf, 数据表
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LE25LB1282TT
2. Status Registers
The status registers read the operating and setting statuses inside the device from outside (status register read) and set
the protect information (status register write). There are 8 bits in total, and “Table 2 Status Registers” gives the
significance of each bit.
Table 2 Status Registers
Bit Name
Bit0 RDY
Bit1 WEN
Bit2 BP0
Bit3 BP1
Bit4 ×
Bit5 ×
Bit6 ×
Bit7 SRWP
Logic
0
1
0
1
0
1
0
1
0
0
0
0
1
Function
Ready
Busy (in write operation)
Write disabled
Write enabled
Block protect information
See status register description on BP0 and BP1
Reserved bit
Reserved bit
Reserved bit
Status register write enabled
Status register write disabled
Power-on time
Information
0
0
Nonvolatile
information
Nonvolatile
information
0
0
0
Nonvolatile
information
2-1. Status Register Read (RDSR)
The contents of the status registers can be read using the status register read command. This command can be executed
even during write operation.
“Figure 5 Status Register READ” shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit7) is the first
to be output, and each time one clock is input, all the other bits up to RDY (bit0) are output in sequence, synchronized
to the falling clock edge. If the clock input is continued after RDY (bit0) has been output, the data is output by returning
to the bit (SRWP) that was first output, after which the output is repeated as long as the clock input is continued. The
data can be read by the status register read command at any time.
Figure 5 Status Register Read
CS
SCK
SI
SO
Mode3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode0
8CLK
05h
(00000101)
Hight Impedance
76 5432107
Status Register Out
No.NA1311-8/14
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