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PDF ( 数据手册 , 数据表 ) LE25CA322

零件编号 LE25CA322
描述 Serial SPI EEPROM
制造商 Sanyo Semicon Device
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LE25CA322 数据手册, 描述, 功能
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Ordering number : ENA1678B
LE25CA322
Serial SPI EEPROM (SPI Bus)
(32Kbit)
Overview
The LE25CA322 is a 32Kbit EEPROM that supports serial peripheral interface (SPI). It realizes high speed operation and
high level reliability by incorporating SANYO’s high performance CMOS EEPROM technology. The interface is
compatible with SPI bus protocol, therefore, it is best suited for applications that require small-scale rewritable nonvolatile
parameter memory. Moreover, the LE25CA322 has a 32 bytes page rewrite function that provides rapid data rewriting.
Features
Capacity
Single supply voltage
Serial interface
Operating clock frequency
Low current dissipation
Page write function
Rewrite time
Number of rewrite times
Data retention period
High reliability
: 32Kbits (4K×8bits)
: 2.7V to 5.5V
: SPI Mode0, Mode3 supported
: 5MHz
: Standby
: 5μA (max.)
: Active (Read) : 3mA (max.)
: Active (Rewrite) : 5mA (max.)
: 32bytes
: 5ms
: 105times/Address, 106 times/Page(Page=32Byte)
: 20years
: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325)
Incorporates a feature to prohibit write operations under low voltage conditions.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
40611 SY/10511 SY/31710 SY 20100219-S00008 No.NA1678-1/14
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LE25CA322 pdf, 数据表
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LE25CA322
Description of Commands and Their Operations
“Table 1 Command Settings” provides a list and overview of the commands. A detailed description of the functions and
operations corresponding to each command is presented below.
1. Read (READ)
Consisting of the first through fourth bus cycles, the read command inputs the 16-bit addresses following (03h), and the
data in the designated addresses is output synchronized to SCK. The data is output from SO on the falling edge of
fourth bus cycle bit0 as a reference. “Figure 4 READ” shows the timing waveforms.
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest
address, the internal address returns to the lowest address (0000h), and data output is continued. By setting the logic
level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO
is in a high-impedance state.
Figure 4 READ
CS
SCK
SI
SO
Mode3 0 1 2 3 4 5 6 7 8 15 16 23 24 25 26 27 28 29 30 31
Mode0
8CLK
03h
(00000011)
Add. Add.
(A15-A8) (A7-A0)
High Impedance
76543 21 07
Data Out(N)
Data Out(N+1)
Addresses A15 to A12 are “don’t care.”
In synchronization with the rising edges of 0 to 23 clock signals, the command is identified and the addresses are
taken in through SI.
In synchronization with the falling edges of 23 clock signal or later, the data is output to SO.
No.NA1678-8/14
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