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PDF ( 数据手册 , 数据表 ) LE24LB642M

零件编号 LE24LB642M
描述 Two Wire Serial Interface EEPROM
制造商 Sanyo Semicon Device
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LE24LB642M 数据手册, 描述, 功能
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Ordering number : ENA1201A
CMOS IC
LE24LB642M Two Wire Serial Interface EEPROM
(64k EEPROM)
Overview
The LE24LB642M is a 2-wire serial interface EEPROM. It realizes high speed and a high level reliability by
incorporating SANYO’s high performance CMOS EEPROM technology. This device is compatible with I2C memory
protocol, therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory.
Functions
Capacity: 64k bits (8k × 8 bits)
Single supply voltage: 1.8V to 5.5V
Interface: Two wire serial interface (I2C Bus*)
Operating clock frequency: 400kHz
Low power consumption
: Standby: 2μA (max)
: Active (Read): 0.5mA (max)
Automatic page write mode: 32 Bytes
Read mode: Sequential read and random read
Erase/Write cycles: 106 cycles (Page writing), 105 cycles (Byte writing)
Data Retention: 20 years
High reliability: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325)
Noise filters connected to SCL and SDA pins
Incorporates a feature to prohibit write operations under low voltage conditions.
* I2C Bus is a trademark of Philips Corporation.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
10511 SY/60408 SY IM 20080415-S00009 No.1201-1/12
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LE24LB642M pdf, 数据表
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LE24LB642M
6-3. Acknowledge polling
Acknowledge polling is used to find out when the EEPROM internal write operation is completed. When the stop
condition is received and the EEPROM starts rewriting, all operations are prohibited, and no response can be given to
the signals sent by the master device. Therefore, in order to find out when the EEPROM internal write operation is
completed, the start condition, device address and write command code are sent from the master device to the
EEPROM (slave device), and the response of the slave device is detected.
In other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is
in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been
completed.
When codes are sent by the master device during acknowledge polling, if a write or random read is to be performed
next, the write command "0" is executed. If a current read or sequential read is to be performed next, the read
command "1" is executed. After the write command "0" is executed and ACK="L" is confirmed, the start
condition/stop condition is entered to cancel the command and change to standby mode.
During Write
During Write
End of Write
SDA
1 0 1 0 S2 S1 S0 W
1 0 1 0 S2 S1 S0 W
1 0 1 0 S2 S1 S0 W
NO ACK
R/W
NO ACK
R/W
ACK
R/W
7 EEPROM read operations
7-1. Current address reading
The address equivalent to the memory address accessed last +1 is held as the internal address of the EEPROM for
both write* and read operations. Therefore, provided that the master device has recognized the position of the
EEPROM address pointer, data can be read from the memory address with the current address pointer without
specifying the word address.
As with writing, current address reading involves receiving the 7-bit device address and read command code “1”
following the start condition, at which time the EEPROM generates an acknowledge signal. After this, the 8-bit data
of the (n+1) address is output serially starting with the highest bits. After the 8 bits have been output, by not sending
an acknowledge signal and inputting the stop condition, the EEPROM completes the read operation and is set to
standby mode.
If the previous read address is the last address, the address for the current address reading is rolled over to become
address 0.
*: If the write data is 1 or more bytes but less than 32 bytes, the current address after page writing is the address
equivalent to the number of bytes to be written in the specified word address +1. If the write data is 32 or more bytes,
it is the designated word address. If the last address (A4-A0=11111b) on the page has been designated by byte write
as the word address, the first address (A4-A0=0000b) on the page serves as the internal address after writing.
Device Address
Data(n+1)
SDA
1 0 1 0 S2 S1 S0 R D7 D6 D5 D4 D3 D2 D1 D0
ACK
R/W
NO ACK
No.1201-8/12
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