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PDF ( 数据手册 , 数据表 ) LE24CBP222

零件编号 LE24CBP222
描述 Two Wire Serial Interface EEPROM
制造商 Sanyo Semicon Device
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LE24CBP222 数据手册, 描述, 功能
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Ordering number : EN*A1812
LE24CBP222
CMOS IC
Power switch integrated triple port EEPROM
Two Wire Serial Interface
(2K+2K EEPROM)
Overview
The power switch integrated triple port EEPROM series consists of two independent banks, and each bank can be
controlled separately using dedicated control pins. The EEPROM also features a control port, which is a third pin
separate from the pins used for the banks, and by accessing the memory areas from this control port, the two-bank
configuration (2K bits + 2K bits) can be used as a pseudo-one-bank configuration (4K bits). Together with the 16-byte
page write function, this enables a reduction in the number of factory write processes.
Furthermore, the EEPROM has a configuration area which is separate from the 2K-bit + 2K-bit area, and by using the
settings stored in this configuration area, it is possible to change the slave address for each port and to set read/write
protection for each port.
The EEPROM also incorporates a power switch circuit with reverse current blocking diodes, supporting different
power voltages among three ports. This product incorporates SANYO's high performance CMOS EEPROM technology
and realizes high-speed operation and high-level reliability. The interface of this product is compatible with the I2C bus
protocol, making it ideal as a nonvolatile memory for small-scale parameter storage.
In addition, this product also supports DDC2TM, so it can also be used as an EDID data storage memory for display
equipment.
Functions
Capacity
: Bank1:2K bits (256 × 8 bits) + Bank2:2K bits (256 × 8 bits)
+ configuration area: 128 bits (16 × 8 bits), 4224 bits in total
Single supply voltage
Interface
: 2.7V to 5.5V. With built-in power switch circuit.
: Two wire serial interface (I2C Bus*), VESA DDC2TM compliant** 3-port access
Operating clock frequency : 400kHz (max)
Low power consumption : Standby: 40μA (max), One-bank read: 8 mA (max.)
* : I2C Bus is a trademark of Philips Corporation.
Continued on next page.
** : DDC and EDID are trademarks of Video Electronics Standard Association (VESA).
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
92910 SY No.1812-1/20
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LE24CBP222
5. Device addressing
For the purposes of communication, the master device in the system generates the start condition for the slave device.
Communication with a particular slave device is enabled by sending along the SDA bus the device address, which is 7
bits long, and the read/write command code, which is 1 bit long, immediately following the start condition.
The upper four bits of the device address are called the device code which, for this product, are fixed at “1010b.”
The 3-bit slave address (SA2, SA1, and SA0 for access from port 1; SB2, SB1, and SB0 for access from port 2; SC2
and SC1for access from the control port) following the device code are stored in the configuration area, and any
values can be set for these addresses. However, the device address to be used to access the configuration area is fixed
at “1011_100b” and cannot be changed.
When the device code input from SDA and the slave addresses are compared with the product’s device code and
configuration area that were set at the mounting stage and found to match, the product sends the acknowledge signal
during the ninth clock cycle period, and initiates the read or write operation in accordance with the read or write
command code. If they do not match, the EEPROM returns to standby mode. When a read operation is performed
immediately after the slave device has been switched, the random read command must be used.
Port 1
Device code
Slave
Address
1 0 1 0 SA2 SA1 SA0 R/W
MSB
Device Address word
LSB
Port 2
1 0 1 0 SB2 SB1 SB0 R/W
MSB
LSB
Control Port
(When you access 1 0 1 0 SC2 SC1 A8* R/W
Bank1, Bank2)
MSB
LSB
*A8=0:Bank1 access
A8=1:Bank2 access
Control Port
(When you access 1 0 1 1 1 0 0 R/W
configuration area)
MSB
LSB
The slave addresses are set as follows when this product is shipped.
(SA2, SA1, SA0) = (0, 0, 0)
(SB2, SB1, SB0) = (0, 0, 0)
(SC2, SC1) = (0, 0)
No.1812-8/20
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LE24CBP222
3) Precautions when turning on the power
This product contains a power-on reset circuit for preventing the inadvertent writing of data when the power is
turned on. The following conditions must be met in order to ensure stable operation of this circuit. No data
guarantees are given in the event of an instantaneous power failure during the internal write operation.
Item
Power rise time
Power off time
Power bottom voltage
VDD
Symbol
tRISE
tOFF
Vbot
min
10
typ
tRISE
max
100
0.2
unit
ms
ms
V
tOFF
Vbot
0V
Notes:
1) The SDA pin must be set to high and the SCL pin to low or high.
2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state.
A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during power rise
After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins set to high.
VDD
SCL
SDA
tLOW
tDH tSU.DAT
VDD
SCL
SDA
tSU.DAT
B. If it is not possible to satisfy the instruction 2 in Note above
After the power has stabilized, software reset must be executed.
C. If it is not possible to satisfy the instructions both 1 and 2 in Note above
After the power has stabilized, the steps in A must be executed, then software reset must be executed.
4) Power switch circuit
This product incorporates a power switch circuit that controls the power supplied to the ports. It prevents reverse flow
of current between power supplies. The circuit also monitors the power status of the ports. The power voltage to the
port to be accessed must always be in operating range of between 2.7V and 5.5V.
5) Noise filter for the SCL and SDA pins
This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 100ns or less are not
recognized because of this function.
6) Function to inhibit writing when supply voltage is low
This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the guaranteed
operating supply voltage range. The data is protected by ensuring that write operations are not started at voltages
(typ.) of 1.3V and below.
No.1812-16/20
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