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PDF ( 数据手册 , 数据表 ) LE24C043

零件编号 LE24C043
描述 Two Wire Serial Interface EEPROM
制造商 Sanyo Semicon Device
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LE24C043 数据手册, 描述, 功能
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Ordering number : ENA1582A
LE24C043
CMOS IC
Two Wire Serial Interface EEPROM
(4k EEPROM)
Overview
The LE24C043 is a 2-wire serial interface 4k Bit EEPROM. It realizes high speed and a high level reliability by
incorporating SANYO’s high performance CMOS EEPROM technology. This device is compatible with I2C memory
protocol, therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory.
Functions
Capacity: 4k bits (256 × 8 bits)
Single supply voltage: 2.7V to 5.5V
Interface: Two wire serial interface (I2C Bus*)
Operating clock frequency: 400kHz
Low power consumption
: Standby: 2μA (max)
: Active (Read): 0.5mA (max)
Automatic page write mode: 16 Bytes
Read mode: Sequential read and random read
Erase/Write cycles: 106 cycles
Data Retention: 20 years
High reliability: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325)
Noise filters connected to SCL and SDA pins
Incorporates a feature to prohibit write operations under low voltage conditions.
Package : MFP8(225mil)
LE24C043M
* I2C Bus is a trademark of Philips Corporation.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
10511 SY/O2109 SY 20091008-S00002 No.1582-1/12
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LE24C043 pdf, 数据表
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LE24C043
6 EEPROM write operation
6-1. Byte writing
When the EEPROM receives the 7-bit device address and write command code "0" after the start condition, it
generates an acknowledge signal. After this, if it 8-bit word address, generates an acknowledge signal, receives the 8-
bit writing data, and generates an acknowledge signal when it receives the stop condition, the rewrite operation of the
EEPROM in the designated memory address will start. Rewriting is completed in the tWC period after the stop
condition. During an EEPROM rewrite operation, no input is accepted and no acknowledge signals are generated.
Word Address
Data
SDA 1 0 1 0 S2 S1 A8 W A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK
R/W
ACK
ACK
6-2. Page writing
This product enables pages with up to 16 bytes to be written. The basic data transfer procedure is the same as for byte
writing: Following the start condition, the 7-bit device address and write command code “0,” word address (n), and
data (n) are input in this order while confirming acknowledge “0” every 9 bits. The page write mode is established if,
after data (n) is input, the write data (n+1) is input without inputting the stop condition. After this, the write data
equivalent to the largest page size can be received by a continuous process of repeating the receiving of the 8-bit
write data and generating the acknowledge signals.
At the point when the write data (n+1) has been input, the lower 4 bits (A0-A3) of the word addresses are
automatically incremented to form the (n+1) address. In this way, the write data can be successively input, and the
word address on the page is incremented each time the write data is input. If the write data exceeds 32 bytes or the
last address of the page is exceeded, the word address on the page is rolled over. Write data will be input into the
same address two or more times, but in such cases the write data that was input last will take effect. Finally, the
EEPROM internal write operation corresponding to the page size for which the write data is received starts from the
designated memory address when the stop condition is received.
Word Address(n)
Data(n)
Data(n+1)
SDA
1 0 1 0 S2 S1 A8 W A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D1 D0
ACK
R/W
ACK
ACK
Data(n+x)
ACK
D7 D6 D1 D0
・・・
ACK
ACK
D7 D6 D1 D0
ACK
D7 D6 D1 D0 D7 D6 D1 D0
ACK
ACK
6-3. Acknowledge polling
Acknowledge polling is used to find out when the EEPROM internal write operation is completed. When the stop
condition is received and the EEPROM starts rewriting, all operations are prohibited, and no response can be given to
the signals sent by the master device. Therefore, in order to find out when the EEPROM internal write operation is
completed, the start condition, device address and write command code are sent from the master device to the
EEPROM (slave device), and the response of the slave device is detected.
In other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is
in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been
completed.
During Write
During Write
End of Write
SDA
1 0 1 0 S2 S1 A8 W
1010
W
1010
W ・・・
NO ACK
R/W
NO ACK
R/W
ACK
R/W
No.1582-8/12
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