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零件编号 | NB3RL02 | ||
描述 | Low Phase-Noise Two-Channel Clock Fanout Buffer | ||
制造商 | ON Semiconductor | ||
LOGO | |||
1 Page
www.DataSheet.co.kr
NB3RL02
Low Phase-Noise
Two-Channel Clock Fanout
Buffer
The NB3RL02 is a low−skew, low jitter 1:2 clock fan−out buffer,
ideal for use in portable end−equipment, such as mobile phones. With
integrated LDO and output control circuitry.
The MCLK_IN pin has an AC coupling capacitor and will directly
accept a square or sine wave clock input, such as a temperature
compensated crystal oscillator (TCXO). The minimum acceptable
input amplitude of the sine wave is 300 mV peak−to−peak.
The two clock outputs are enabled by control inputs CLK_REQ1
and CLK_REQ2.
The NB3RL02 has an integrated Low−Drop−Out (LDO) voltage
regulator which accepts input voltages from 2.3 V to 5.5 V and outputs
1.8 V at Iout = 50 mA. This 1.8 V supply is externally available to
provide regulated power to peripheral devices, such as a TCXO.
The adaptive clock output buffers offer controlled slew−rate over a
wide capacitive loading range which minimizes EMI emissions,
maintains signal integrity, and minimizes ringing caused by signal
reflections on the clock distribution lines.
The NB3RL02 is offered in a 0.4 mm pitch wafer−level−chip−scale
(WLCS) package (0.8 mm x 1.6 mm) and is optimized for very low
standby current consumption.
Features
• Low Additive Noise:
♦ −149 dBc/Hz at 10 kHz Offset Phase Noise
♦ 0.37 ps (rms) Output Jitter
• Limited Output Slew Rate for EMI Reduction
(1 ns to 5 ns/Rise/Fall Time for 10−50 pF Loads)
• Regulated 1.8 V Output Supply Available for External Clock Source,
ie. TCX0
• Ultra−Small Package:
♦ 8−ball: 0.4 mm Pitch WLCS (0.8 mm x 1.6 mm)
• ESD Performance Exceeds JESD 22
♦ 2000 V Human−Body Model (A114−A)
♦ 200 V Machine Model (A115−A)
♦ 1000 V Charged−Device Model (JESD22−C101−A Level III)
• These are Pb−Free Devices
Applications
• Cellular Phones
• Global Positioning Systems (GPS)
http://onsemi.com
MARKING
DIAGRAMS
WLCSP8
CASE 499BQ
RLYYWW
G
RL = Specific Device Code
YY = Year
WW = Work Week
G = Pb−Free Package
LOGIC DIAGRAM
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
July, 2011 − Rev. 1
1
Publication Order Number:
NB3RL02/D
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NB3RL02
PACKAGE DIMENSIONS
WLCSP8, 1.57x0.77
CASE 499BQ−01
ISSUE O
PIN A1
REFERENCE
D
ÈÈÈÈ
AB
E
2X 0.10 C
2X 0.10 C TOP VIEW
0.10 C
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
MILLIMETERS
DIM MIN MAX
A −−− 0.50
A1 0.13 0.17
b 0.21 0.25
D 0.77 BSC
E 1.57 BSC
e 0.40 BSC
8X 0.05 C
NOTE 3
SIDE VIEW
A1
C
SEATING
PLANE
8X b
0.05 C A B
0.03 C
D
C
B
e/2
e
e
RECOMMENDED
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
0.40
PITCH
0.40
PITCH
8X
0.23
DIMENSIONS: MILLIMETERS
A
12
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
8
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB3RL02/D
Datasheet pdf - http://www.DataSheet4U.net/
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页数 | 8 页 | ||
下载 | [ NB3RL02.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
NB3RL02 | Low Phase-Noise Two-Channel Clock Fanout Buffer | ON Semiconductor |
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