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PDF ( 数据手册 , 数据表 ) K4B2G1646C

零件编号 K4B2G1646C
描述 2Gb C-die DDR3 SDRAM
制造商 Samsung semiconductor
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K4B2G1646C 数据手册, 描述, 功能
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Rev. 1.11, Nov. 2010
K4B2G1646C
2Gb C-die DDR3 SDRAM Only x16
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2010 Samsung Electronics Co., Ltd. All rights reserved.
-1-
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K4B2G1646C pdf, 数据表
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K4B2G1646C
datasheet
Rev. 1.11
DDR3 SDRAM
4. Input/Output Functional Description
[ Table 3 ] Input/Output function description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and
output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or
Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become
stable during the power on and initialization sequence, it must be maintained during all operations (including Self-
Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT
and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on
systems with multiple Ranks. CS is considered part of the command code.
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode
Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is pro-
grammed to disable ODT.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
(DMU), (DML)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-
dent with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of
DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.
BA0 - BA2
Input
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS cycle.
A0 - A13
Input
Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands
to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions,
see below)
The address inputs also provide the op-code during Mode Register Set commands.
A10 / AP
Input
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-
formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.
A12 / BC
Input
Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-
formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details
RESET
DQ
Input
Input/Output
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.
RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and
20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.
Data Input/ Output: Bi-directional data bus.
DQS, (DQS)
Input/Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the
x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data
strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide dif-
ferential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
TDQS, (TDQS)
Output
Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When
disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/
x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1.
NC No Connect: No internal electrical connection is present.
VDDQ
VSSQ
VDD
VSS
VREFDQ
VREFCA
ZQ
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DQ Power Supply: 1.5V +/- 0.075V
DQ Ground
Power Supply: 1.5V +/- 0.075V
Ground
Reference voltage for DQ
Reference voltage for CA
Reference Pin for ZQ calibration
NOTE : Input only pins (BA0-BA2, A0-A13, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.
-8-
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K4B2G1646C
datasheet
Rev. 1.11
DDR3 SDRAM
9. AC & DC Output Measurement Levels
9.1 Single-ended AC & DC Output Levels
[ Table 14 ] Single-ended AC & DC output levels
Symbol
Parameter
DDR3-800/1066/1333/1600/1866/2133
Units
NOTE
VOH(DC)
DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT + 0.1 x VDDQ
V1
VOL(AC)
AC output low measurement level (for output SR)
VTT - 0.1 x VDDQ
V1
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40and an effective test
load of 25to VTT=VDDQ/2.
9.2 Differential AC & DC Output Levels
[ Table 15 ] Differential AC & DC output levels
Symbol
Parameter
DDR3-800/1066/1333/1600/1866/2133
Units
NOTE
VOHdiff(AC)
VOLdiff(AC)
AC differential output high measurement level (for output SR)
AC differential output low measurement level (for output SR)
+0.2 x VDDQ
-0.2 x VDDQ
V1
V1
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40and an effective test
load of 25to VTT=VDDQ/2 at each of the differential outputs.
9.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in Table 16 and Figure 6.
[ Table 16 ] Single-ended output slew rate definition
Description
Measured
From
To
Defined by
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
VOH(AC)-VOL(AC)
Delta TRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
VOH(AC)-VOL(AC)
Delta TFse
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 17 ] Single-ended output slew rate
Parameter
Symbol
DDR3-800
Min Max
DDR3-1066
Min Max
DDR3-1333
Min Max
DDR3-1600
Min Max
DDR3-1866
Min Max
DDR3-2133
Units
Min Max
Single ended output slew rate SRQse 2.5 5 2.5 5 2.5 5 2.5 5 2.5 51) 2.5 51) V/ns
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ
signals in the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the
remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
VOH(AC)
VTT
VOL(AC)
delta TFse
delta TRse
Figure 6. Single-ended Output Slew Rate Definition
- 16 -
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