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PDF ( 数据手册 , 数据表 ) PE12016G

零件编号 PE12016G
描述 (PE12016G / PE12024G) Incremental Encoder
制造商 Productivity Engineering
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PE12016G 数据手册, 描述, 功能
www.DataSheet4U.net
PE12016G / PE12024G
December 15, 2005 Version 1.7
Incremental Encoder
Features:
Functional and pincompatible with obsolete
TI CF32007NW/NT / THCT12016 /
THCT 12024 / LS2000
5 V and 3.3 V Operation
0.6u CMOS Process
Direction discriminator
Pulse width measurement
Frequency measurement
Cascadable (PE12016G only)
TTL compatible
8 Bit parallel tristateable Bus
Simple read & write procedure
High speed 20 MHz clock operation
PE12016G ONLY: 1:1 Replacement for
LS2000AN
PE12024G ONLY: 24-Bit resolution,
separate UA0 counter reset
WEEE & RoHS Compliant according
DIRECTIVE 2002/95/EC
(Green Package Material)
PE12016G
PDIP28-600 Mil
1
CS
28
VCC
RD UP
D0 DOWN
D1 WE
D2 RESET
D3 A0
GND
CLK
D4 UA2
D5 UA1
D6 M0
D7 M1
BORROW
M2
CARRY READY
GND KLI-KLO
14 15
PE12024G
PDIP24-300 Mil
1 24
CS VCC
RD UA0
D0 A1
D1 WE
D2 RESET
D3 A0
GND CLK
D4 UA2
D5 UA1
D6 M0
D7 M1
GND
12
M2
13
Description:
The PE12016G/12024G INCREMENTAL
ENCODER INTERFACE can independently
determine the direction or displacement of a
mechanical device or axis based on two input
signals from transducers in quadrature.
Alternatively, it can measure a pulse width using
a known clock rate, or a frequency, by counting
input pulses over a
known time interval. It includes one 16-bit or 24-
bit counter which may also be used separately
(PE12016G only). The PE12016G may be
cascaded to provide accuracy greater than 16-
bits. Both devices are designed for use in many
microprocessor-based systems.
December 15, 2005 (Version 1.7)
Seite 1 / 25
PE12016G/24G







PE12016G pdf, 数据表
www.DataSheet4U.net
PE12016G / PE12024G
December 15, 2005 Version 1.7
Incremental Encoder
In pulse width mode, the minimum time that can be measured is:
Tmin = 2 (To) (Accuracy is +/- To)
Fig. 6: Pulse Width Measurement
MODE 7: Frequency Measurement Mode
In Mode 7, Ua1 is the signal of unknown
frequency to be measured; Ua2 is a gate signal
of known width. A low to high transition of Ua2
enables counting at the frequency of Ua1. When
the gate (Ua2) goes low, counting is disabled.
The value of the counter is loaded into the output
register, /KLI-KLO is pulled low (PE12016G
only), and the counter is then cleared. See
Figure 8.
Fig. 7: Frequency Measurement
December 15, 2005 (Version 1.7)
Seite 8 / 25
PE12016G/24G







PE12016G equivalent, schematic
www.DataSheet4U.net
PE12016G / PE12024G
December 15, 2005 Version 1.7
Incremental Encoder
Switching Characteristics, (Vcc=Min, Temperature +70 Degrees)
Symbol
Parameter
Test Conditions
See appendix A
(test pattern)
Tdd1
Access time, /RD and CLK to
data output valid
(Mode = 0 to 5)
Tdd2
Access time, /RD to data
output valid
Mode = 0 to 5 2nd byte or 3rd
byte*
Mode = 6 to 7 both bytes, or all
three bytes (PE12024G only)
Propagation delay /RD, /WE or
Thr /CS inactive to /READY From CS
(PE12016G only)
Tdr Propagation delay CLK to
/READY low (PE12016G only)
Tduc
Propagation delay /UP or
/DOWN rising edge to /CARRY
or /BORROW rising edge
From /UP to
/CARRY
(PE12016G only)
Tdcc
Propagation delay from CLK to
/CARRY or /BORROW rising
edge (PE12016G only)
From /CLK to
/CARRY or
from /CLK to
/BORROW
Tdco
Propagation delay CLK falling
edge to /KLI-KLO falling edge
(PE12016G only)
Tdcb
Propagation delay CLK rising From /CLK to
edge to /CARRY or /BORROW
/CARRY or
rising edge (PE12016G only)
/BORROW
Ted
Enable Time /RD and /CS low
to D0-D7
Twco
/KLI-KLO low output pulse
width (PE12016G only)
Twcb
/CARRY or /BORROW low
output pulse width (PE12016G
only)
Twcc
/CARRY or /BORROW low
output pulse width (PE12016G
only)
Thdr
Release time,
DATA after /RD, /CS
From /CS
DATA >0116 ZZ16
MIN
0
TYP MAX Units
65 ns
45 ns
20 ns
30 ns
35 ns
25 ns
55 ns
25 ns
65
Tc2
ns
ns
Twud
ns
Tc2 ns
45 ns
December 15, 2005 (Version 1.7)
Seite 16 / 25
PE12016G/24G










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