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零件编号 | V201B1-L03 | ||
描述 | LCD Module | ||
制造商 | CHI MEI | ||
LOGO | |||
1 Page
Issued Date: Nov. 28 2006
Model No.: V201B1 - L03
Approval
TFT LCD Approval Specification
MODEL NO.: V201B1 - L03
Customer:
Approved by:
Note:
Sony Corporation
LCD TV Head Division
VP ພၼ
QRA Dept.
Approval
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DDI
Approval
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TVHD / PDD
DDII
Approval
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DDIII
Approval
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LCD TV Marketing and Product Management Division
Product Manager
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www.DataSheet4U.net
1
Version 2.0
Issued Date: Nov. 28 2006
Model No.: V201B1 - L03
Approval
Note (3) The specified power supply current is under the conditions at Vcc = 5 V, Ta = 25 ± 2 ºC, fv = 60 Hz,
whereas a power dissipation check pattern below is displayed.
a. White Pattern
b. Black Pattern
Active Area
c. Vertical Stripe Pattern
Active Area
Active Area
RGB RGB
BRGB RGBR
BRGB RGBR
RGB RGB
3.2 BACKLIGHT INVERTER UNIT
3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 ± 2 ºC)
Parameter
Lamp Voltage
Lamp Current
Lamp Starting Voltage
Operating Frequency
Lamp Life Time
Symbol
VW
IL
VS
FO
LBL
Min.
-
4.8
-
-
40
50,000
Value
Typ.
1610
5.3
-
-
-
60,000
Max.
-
5.8
2400
2250
70
-
Unit
VRMS
mARMS
VRMS
VRMS
KHz
Hrs
Note
IL = 5.3mA
(1)
(2), Ta = 0 ºC
(2), Ta = 25 ºC
(3)
(4)
Note (1) Lamp current is measured by current probe (Tekronix P6022) with Tekronix oscilloscope as shown
below, and lamp current IL = Irms:(This is temporary measurement method.)
Electric current direction of current probe
8
Version 2.0
Issued Date: Nov. 28, 2005
Model No.: V201B1 - L03
Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
LVDS Receiver Clock
Item Symbol Min. Typ. Max. Unit
Frequency
1/Tc 65
86
88 MHZ
Input cycle to Trcl
cycle Jitter
-
- 200 ps
Note
LVDS Receiver Data
Setup Time
Hold Time
Tlvsu
Tlvhd
600
600
-
-
- ps
- ps
Frame Rate
Fr5
Fr6
47
57
50
60
53 Hz
63 Hz
Vertical Active Display Term Total
Tv 778 795 888 Th Tv=Tvd+Tvb
Display
Tvd 768 768 768 Th
-
Blank
Tvb 10
27 120 Th
-
Total
Horizontal Active Display Term Display
Th 1436 1798 1936 Tc Th=Thd+Thb
Thd 1366 1366 1366 Tc
-
Blank
Thb 70
432 570 Tc
-
Note (1) Since this module is operated in DE only mode, Hsync and Vsync input signals should be set to
low logic level. Otherwise, this module would operate abnormally.
(2) Please refer to 5.1 for detail information.
INPUT SIGNAL TIMING DIAGRAM
DE
Th
Tvd
Tv
Tvb
DCLK
DE
DATA
Tc
Thb
Thd
Valid display data (1366 clocks)
16
Version 2.0
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页数 | 29 页 | ||
下载 | [ V201B1-L03.PDF 数据手册 ] |
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