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PDF ( 数据手册 , 数据表 ) CY14C064I

零件编号 CY14C064I
描述 64-Kbit (8 K x 8) Serial (I2C) nvSRAM
制造商 Cypress Semiconductor
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CY14C064I 数据手册, 描述, 功能
PRELIMINARY
CY14C064I
CY14B064I, CY14E064I
64-Kbit (8 K × 8) Serial (I2C) nvSRAM
with Real Time Clock
64-Kbit (8 K × 8) Serial (I2C) nvSRAM with Real Time Clock
Features
64-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 8 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
RECALL
RECALL)
to
or
SRAM initiated on power-up (Power-Up
by I2C command (Software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 °C
Real Time Clock (RTC)
Full-featured RTC
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 µA (typical)
High-speed I2C interface
Industry standard 100 kHz and 400 kHz speed
Fast mode Plus 1 MHz speed
High speed: 3.4 MHz
Zero cycle delay reads and writes
Write protection
Hardware protection using Write Protect (WP) pin
Software block protection for one-quarter, one-half, or entire
array
I2C access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Low power consumption
Average active current of 1 mA at 3.4 MHz operation
Average standby mode current of 250 µA
Sleep mode current of 8 µA
Industry standard configurations
Operating voltages:
• CY14C064I : VCC = 2.4 V to 2.6 V
• CY14B064I : VCC = 2.7 V to 3.6 V
• CY14E064I : VCC = 4.5 V to 5.5 V
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C064I/CY14B064I/CY14E064I combines a
64-Kbit nvSRAM[1] with a full-featured RTC in a monolithic
integrated circuit with serial I2C interface. The memory is
organized as 8 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cells provide highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down.
On power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL
operations can also be initiated by the user through I2C
commands.
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Power Control
Block
Sleep
Serial Number
8x8
Manufacture ID/
Product ID
Memory Control Register
Command Register
SDA
SCL
A2, A1, A0
WP
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
RTC Slave
Memory
Address and Data
Control
QuantrumTrap
8Kx8
SRAM
8Kx8
STORE
RECALL
X in
INT/SQW
Xout
RTC Control Logic
Registers
Counters
Note
1. Serial (I2C) nvSRAM will be referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-68169 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 1, 2011
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CY14C064I pdf, 数据表
PRELIMINARY
CY14C064I
CY14B064I, CY14E064I
Figure 9. Control Registers Slave Device Address
handbook, halfpMagSe B
00
LSB
1 1 A2 A1 A0 R/W
Slave ID
Device Select
Table 2. Control Registers Map
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0xAA
Description Read/Write
Details
Memory
Control
Register
Read/Write Contains Block
Protect bits and Serial
Number lock bit
Serial Number Read/Write Programmable Serial
8 bytes (Read only Number. Locked by
when SNL setting the Serial
is set) Number lock bit in the
Memory Control
Register to ‘1’.
Device ID
Read only Device ID is factory
programmed
Reserved
Command
Register
Reserved
Write only
Reserved
Allows commands for
STORE, RECALL,
AutoStore
Enable/Disable,
SLEEP Mode
Memory Control Register
The Memory Control Register contains the following bits:
Table 3. Memory Control Register Bits
Bit 7
0
Bit 6
SNL
(0)
Bit 5
0
Bit 4
0
Bit 3
BP1
(0)
Bit 2
BP0
(0)
Bit 1
0
Bit 0
0
BP1:BP0: Block protect bits are used to protect 1/4, 1/2 or full
memory array. These bits can be written through a write
instruction to the 0x00 location of the Control Register Slave
device. However, any STORE cycle transfers SRAM data into
a nonvolatile cell regardless of whether or not the block is
protected. The default value shipped from the factory for BP0
and BP1 is ‘0’.
Table 4. Block Protection
Level
0
1/4
1/2
1
BP1:BP0
00
01
10
11
Block Protection
None
0x1800-0x1FFF
0x1000-0x1FFF
0x0000-0x1FFF
S/N Lock (SNL) Bit: Serial Number Lock bit (SNL) is used to
lock the serial number. After the bit is set to ‘1’, the serial number
registers are locked and no modification is allowed. This bit
cannot be cleared to ‘0’. The serial number is secured on the
next STORE operation (Software STORE or AutoStore). If
AutoStore is not enabled, user must perform the Software
STORE operation to secure the lock bit status. If a STORE was
not performed, the serial number lock bit will not survive the
power cycle. The default value shipped from the factory for SNL
is ‘0’.
Command Register
The Command Register resides at address ‘AA’ of the Control
Registers Slave device. This is a write only register. The byte
written to this register initiates a STORE, RECALL, AutoStore
Enable, AutoStore Disable, and Sleep mode operation as listed
in Table 5. The section Executing Commands Using Command
Register on page 19 explains how you can execute Command
Register bytes.
Table 5. Command Register Bytes
Data Byte
[7:0]
0011 1100
0110 0000
Command
Description
STORE
RECALL
STORE SRAM data to nonvolatile
memory
RECALL data from nonvolatile
memory to SRAM
0101 1001
0001 1001
1011 1001
ASENB
ASDISB
SLEEP
Enable AutoStore
Disable AutoStore
Enter Sleep Mode for low power
consumption
STORE: Initiates nvSRAM Software STORE. The nvSRAM
cannot be accessed for tSTORE time after this instruction has
been executed. When initiated, the device performs a STORE
operation regardless of whether or not a write has been
performed since the last NV operation. After the tSTORE cycle
time is completed, the SRAM is activated again for read/write
operations.
RECALL: Initiates nvSRAM Software RECALL. The nvSRAM
cannot be accessed for tRECALL time after this instruction has
been executed. The RECALL operation does not alter the data
in the nonvolatile elements. A RECALL may be initiated in two
ways: Hardware RECALL, initiated on power-up; and Software
RECALL, initiated by a I2C RECALL instruction.
ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be
accessed for tSS time after this instruction has been executed.
This setting is not nonvolatile and needs to be followed by a
manual STORE sequence if this is desired to survive the power
cycle. The part comes from the factory with AutoStore Enabled.
ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot
be accessed for tSS time after this instruction has been
executed. This setting is not nonvolatile and needs to be
followed by a manual STORE sequence if this is desired to
survive the power cycle.
Note If AutoStore is disabled and VCAP is not required, it is
required that the VCAP pin is left open. VCAP pin must never be
connected to ground. Power Up RECALL operation cannot be
disabled in any case.
Document #: 001-68169 Rev. **
Page 8 of 41
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CY14C064I equivalent, schematic
PRELIMINARY
CY14C064I
CY14B064I, CY14E064I
Control Registers Slave
The following sections describe the data transfer sequence
required to perform read or write operations from Control
Registers Slave.
Write Control Registers
To write the Control Registers Slave, the master transmits the
Control Registers Slave address after generating the START
condition. The write sequence continues from the address
location specified by the master till the master generates a STOP
condition or the last writable address location.
If a non-writable address location is accessed for write operation
during a normal write or a burst, the slave generates a NACK
after the data byte is sent and the write sequence terminates.
Any following data bytes are ignored and the address counter is
not incremented.
If a write operation is performed on the Command Register
(0xAA), the following current read operation also begins from the
first address (0x00) as in this case, the current address is an
out-of-bound address. The address is not incremented and the
next current read operation begins from this address location. If
a write operation is attempted on an out-of-bound address
location, the nvSRAM sends a NACK immediately after the
address byte is sent.
Further, if the serial number is locked, only two addresses (0xAA
or Command Register, and 0x00 or Memory Control Register)
are writable in the Control Registers Slave. On a write operation
to any other address location, the device will acknowledge
command byte and address bytes but it returns a NACK from the
control Registers Slave for data bytes. In this case, the address
will not be incremented and a current read will happen from the
last acknowledged address.
The nvSRAM Control Registers Slave sends a NACK when an
out of bound memory address is accessed for write operation, by
the master. In such a case, a following current read operation
begins from the last acknowledged address.
Figure 29. Single-Byte Write into Control Registers
By Master
SDA Line
By nvSRAM
S
T
A Control Registers
R Slave Address
T
S 0 0 1 1 A2 A1 A0 0
Control Register Address
A
A
Data Byte
S
T
0
P
P
A
Figure 30. Multi-Byte Write into Control Registers
By Master
SDA Line
By nvSRAM
S
T
A Control Registers
R Slave Address
T
S 0 0 1 1 A2 A1 A0 0
Control Register Address
A
A
Data Byte
A
Data Byte N
S
T
0
P
P
A
Document #: 001-68169 Rev. **
Page 16 of 41
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