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PDF ( 数据手册 , 数据表 ) W83627THG

零件编号 W83627THG
描述 Winbond LPC I/O
制造商 Winbond
LOGO Winbond LOGO 


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W83627THG 数据手册, 描述, 功能
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W83627THF
W83627THG
Winbond LPC I/O
Date: Sep. 26, 2006 Revision: 1.22







W83627THG pdf, 数据表
W83627THF/W83627THG
1. GENERAL DESCRIPTION
W83627THF is a Winbond LPC I/O product. It integrates the following major peripheral functions in a
chip: the disk driver adapter (FDC), Serial port (UART), Parallel port (SPP/EPP/ECP), Keyboard
controller (KBC), SIR, Game port, MIDI port, Hardware Monitor, ACPI, On Now Wake-Up features.
The disk drive adapter functions of W83627THF include a floppy disk drive controller compatible with
the industry standard 82077/765, data separator, write pre-compensation circuit, decode logic, data
rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide
range of functions integrated onto the W83627THF greatly reduces the number of components
required for interfacing with floppy disk drives. The W83627THF supports four 360K, 720K, 1.2M,
1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s, 1 Mb/s, and 2
Mb/s.
The W83627THF provides two high-speed serial communication ports (UARTs), one of which
supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a
programmable baud rate generator, complete modem control capability, and a processor interrupts
system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed
with baud rates of 230k, 460k, or 921k bps, which support higher speed modems. In addition, the
W83627THF provides IR functions: IrDA 1.0 (SIR for 1.152K bps)
The W83627THF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and
also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port
interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or
two external floppy disk drives to be connected.
The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
demand of Windows 95/98TM, which makes system resource allocation more efficient than ever.
The W83627THF provides functions that complies with ACPI (Advanced Configuration and Power
Interface), which includes support of legacy and ACPI power management through PME# or PSOUT#
function pins. For OnNow keyboard Wake-Up, OnNow mouse Wake-Up. The W83627THF also
has auto power management to reduce the power consumption.
The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable
ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEYTM -2,
Phoenix MultiKey/42TM, or customer code.
The W83627THF provides a set of flexible I/O control functions to the system designer through a set
of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually
configured to provide a predefined alternate function.
Publication Release Date: September 26, 2006
- 1 - Revision 1.2







W83627THG equivalent, schematic
W83627THF/W83627THG
PIN DESCRIPTION, continued.
TYPE
DESCRIPTION
OD12p3 3.3V open-drain output pin with 12 mA sink capability
INt TTL level input pin
INtp3
3.3V TTL level input pin
INtd TTL level input pin with internal pull down resistor
INtu TTL level input pin with internal pull up resistor
INts TTL level Schmitt-trigger input pin
INtsp3 3.3V TTL level Schmitt-trigger input pin
INc CMOS level input pin
INcd CMOS level input pin with internal pull down resistor
INcs CMOS level Schmitt-trigger input pin
INcsu
CMOS level Schmitt-trigger input pin with internal pull up resistor
AOUT Analog output
AIN Analog input
3.1 LPC Interface
SYMBOL
CLKIN
PME#
PCICLK
LDRQ#
SERIRQ
LAD[3:0]
LFRAME#
LRESET#
PIN I/O
FUNCTION
18
INt
System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz input.
19 OD8 erated P
21 INtsp3 PCI 33 MHz clock input.
22 OUT12tp3 Encoded DMA Request signal.
23 I/OD12tp3 Serial IRQ input/Output.
24-27
I/O12tp3
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
29 INtsp3 Indicates start of a new cycle or termination of a broken cycle.
30 INtsp3 Reset signal. It can connect to PCIRST# signal on the host.
Publication Release Date: September 26, 2006
- 9 - Revision 1.2










页数 30 页
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