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PDF ( 数据手册 , 数据表 ) D75104

零件编号 D75104
描述 UPD75104
制造商 NEC
LOGO NEC LOGO 


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D75104 数据手册, 描述, 功能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75104, 75106, 75108
4-BIT SINGLE-CHIP MICROCOMPUTER
www.DataSheet4U.net
DESCRIPTION
µPD75108 is a 4-bit single-chip microcomputer integrating timer/event counters, serial interface, and vector
interrupt function, in addition to a CPU, ROM, RAM, and I/O ports, on a single chip. Operating at high speeds,
the microcomputer allows data to be manipulated in units of 1, 4, or 8 bits. In addition, various bit manipulation
instructions are provided to reinforce I/O manipulation capability. Equipped with I/Os for interfacing with
peripheral circuits operating on a different supply voltage, outputs that can directly drive LEDs, and analog
inputs, µPD75108 is suitable for controlling such systems as VTRs, acoustic products, button telephones, radio
communications equipment, and printers. A pin-compatible EPROM model is also available for evaluation of
system development and small-scale production of application systems.
Detailed functions are described in the following user’s manual. Be sure to read it for designing.
µPD751XX Series User’s Manual: IEM-922
FEATURES
Internal memory
• Program memory (ROM)
: 8068 × 8 bits (µPD75108)
: 6016 × 8 bits (µPD75106)
: 4096 × 8 bits (µPD75104)
• Data memory (RAM)
: 512 × 4 bits (µPD75108)
: 320 × 4 bits (µPD75106, 75104)
New architecture “75X series” rivaling 8-bit microcomputers
43 systematically organized instructions
• A wealth of bit manipulation instructions
• 8-bit data transfer, compare, operation, increment, and decrement instructions
• 1-byte relative branch instructions
• GETI instruction executing 2-/3-byte instruction with one byte
High speed. Minimum instruction execution time: 0.95 µs (at 4.19 MHz), 5 V
Power-saving, instruction time change function: 0.95 µs/1.91 µs/15.3 µs (at 4.19 MHz)
I/O port pins as many as 58
Three channels of 8-bit timers
8-bit serial interface
Multiplexed vector interrupt function
Model with PROM is available: µPD75P108B (One-time PROM, EPROM)
Unless there are differences among µPD75104, 75106, and 75108 functions, µPD75108 is treated as the
representative model throughout this manual.
The information in this document is subject to change without notice.
Document No. IC-2520B
(O. D. No. IC-6906B)
Date Published January 1994 P
Printed in Japan
The mark 5 shows major revised points.
© NEC Corporation 1989







D75104 pdf, 数据表
TI0
PTO0/P20
TI1
PTO1/P21
SI/P03
SO/P02
SCK/P01
BASIC
INTERVAL
TIMER
INTBT
TIMER/EVENT
COUNTER
#0
INTT0
TIMER/EVENT
COUNTER
#1
INTT1
SERIAL
INTERFACE
INTSIO
PROGRAM
COUNTER*
ROM
PROGRAM
MEMORY
8064 × 8BITS
: µPD75108
6016 × 8BITS
: µPD75106
4096 × 8BITS
: µPD75104
ALU
CY SP (8)
BANK
DECODE
AND
CONTROL
GENERAL REG.
RAM
DATA MEMORY
512 × 4BITS
: µPD75108
320 × 4BITS
: µPD75106, 75104
INT0/P10
INT1/P11
INT2/P12
INT3/P13
INT4/P00
INTERRUPT
CONTROL
PTH00-PTH03 4
PROGRAM-
MABLE
THRESHOLD
PORT #0
CLOCK
OUTPUT
CONTROL
f XX /2N
CLOCK
CLOCK
DIVIDER GENERATOR
STAND BY
CONTROL
CPU CLOCK
Φ
PCL/P22
*: 13 bits: µPD75106, 75108
12 bits: µPD75104
X1 X2
V DD V SS RESET
BIT SEQ.
BUFFER (16)
PORT 0
PORT 1
4 P00 - P03
4 P10 - P13
PORT 2 4 P20 - P23
PORT 3 4 P30 - P33
PORT 4 4 P40 - P43
PORT 5 4 P50 - P53
PORT 6 4 P60 - P63
PORT 7 4 P70 - P73
PORT 8 4 P80 - P83
PORT 9 4 P90 - P93
PORT 12 4 P120 - P123
PORT 13 4 P130 - P133
PORT 14 4 P140 - P143







D75104 equivalent, schematic
µPD75104, 75106, 75108
(b) µ PD75106
Address
765
0000H MBE RBE 0 Internal reset start address (upper 5 bits)
Internal reset start address (lower 8 bits)
0002H MBE RBE 0 INTBT/INT4 start address (upper 5 bits)
INTBT/INT4 start address (lower 8 bits)
0004H MBE RBE 0 INT0/INT1 start address (upper 5 bits)
INT0/INT1 start address (lower 8 bits)
0006H MBE RBE 0 INTSIO start address (upper 5 bits)
INTSIO start address (lower 8 bits)
0008H MBE RBE 0 INTT0 start address (upper 5 bits)
INTT0 start address (lower 8 bits)
000AH MBE RBE 0 INTT1 start address (upper 5 bits)
INTT1 start address (lower 8 bits)
0020H
007FH
0080H
GETI instruction reference table
0
CALLF
! faddr
instruction
entry
address
CALL ! addr
instruction
subroutine
entry address
BRCB
! caddr
instruction
branch
address
BR ! addr
instruction
branch address
BR $addr
instruction
relational
branch address
(–15 to +16)
07FFH
0800H
Branch destination
address and
subroutine entry
address for
GETI instruction
0FFFH
1000H
177FH
BRCB ! caddr
instruction
branch address
Fig. 4-1 Program Memory Map (2/3)
Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC
with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.
16










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