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PDF ( 数据手册 , 数据表 ) ADRF6703

零件编号 ADRF6703
描述 1550 MHz to 2650 MHz Quadrature Modulator
制造商 Analog Devices
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ADRF6703 数据手册, 描述, 功能
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1550 MHz to 2650 MHz Quadrature Modulator with
2100 MHz to 2600 MHz Frac-N PLL and Integrated VCO
ADRF6703
FEATURES
IQ modulator with integrated fractional-N PLL
RF output frequency range: 1550 MHz to 2650 MHz
Internal LO frequency range: 2100 MHz to 2600 MHz
Output P1dB: 14.2 dBm @ 2140 MHz
Output IP3: 33.2 dBm @ 2140 MHz
Noise floor: −159.6 dBm/Hz @ 2140 MHz
Baseband bandwidth: 750 MHz (3 dB)
SPI serial interface for PLL programming
Integrated LDOs and LO buffer
Power supply: 5 V/240 mA
40-lead 6 mm × 6 mm LFCSP
APPLICATIONS
Cellular communications systems
GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE
Broadband wireless access systems
Satellite modems
GENERAL DESCRIPTION
The ADRF6703 provides a quadrature modulator and
synthesizer solution within a small 6 mm × 6 mm footprint
while requiring minimal external components.
The ADRF6703 is designed for RF outputs from 1550 MHz to
2650 MHz. The low phase noise VCO and high performance
quadrature modulator make the ADRF6703 suitable for next
generation communication systems requiring high signal
dynamic range and linearity. The integration of the IQ
modulator, PLL, and VCO provides for significant board
savings and reduces the BOM and design complexity.
The integrated fractional-N PLL/synthesizer generates a 2× fLO
input to the IQ modulator. The phase detector together with an
external loop filter is used to control the VCO output. The VCO
output is applied to a quadrature divider. To reduce spurious
components, a sigma-delta (Σ-Δ) modulator controls the
programmable PLL divider.
The IQ modulator has wideband differential I and Q inputs,
which support baseband as well as complex IF architectures.
The single-ended modulator output is designed to drive a
50 Ω load impedance and can be disabled.
The ADRF6703 is fabricated using an advanced silicon-
germanium BiCMOS process. It is available in a 40-lead,
exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP package.
Performance is specified from −40°C to +85°C. A lead-free
evaluation board is available.
Table 1.
Part No.
ADRF6702
ADRF6703
Internal LO
Range
1550 MHz
2150 MHz
2100 MHz
2600 MHz
±3 dB RFOUT
Balun Range
1200 MHz
2400 MHz
1550 MHz
2650 MHz
VCC7
34
VCC6
29
VCC5
27
FUNCTIONAL BLOCK DIAGRAM
VCC4 VCC3 VCC2 VCC1
22 17
10
1
LOSEL 36
ADRF6703
LON 37
LOP 38
BUFFER
DIVIDER
÷2
BUFFER
DATA 12
CLK 13
LE 14
REFIN 6
MUXOUT 8
SPI
INTERFACE
×2
MUX
÷2
÷4
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
21 TO 123
TEMP
SENSOR
+
PHASE
FREQUENCY
DETECTOR
PRESCALER
÷2
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
4 7 11 15 20 21 23 25 28 30 31 35 24
5
GND
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
NC RSET
Figure 1.
2:1
MUX
VCO
CORE
3 39 16 26
CP VTUNE ENOP RFOUT
÷2
0/90
40 DECL3
9 DECL2
2 DECL1
18 QP
19 QN
32 IN
33 IP
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.







ADRF6703 pdf, 数据表
ADRF6703
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC1 1
DECL1 2
CP 3
GND 4
RSET 5
REFIN 6
GND 7
MUXOUT 8
DECL2 9
VCC2 10
PIN 1
INDICATOR
ADRF6703
TOP VIEW
(Not to Scale)
30 GND
29 VCC6
28 GND
27 VCC5
26 RFOUT
25 GND
24 NC
23 GND
22 VCC4
21 GND
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A
LOW IMPEDANCE GROUND PLANE.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1, 10, 17, 22, 27, 29, 34
VCC1, VCC2, VCC3,
VCC4, VCC5, VCC6,
VCC7
2 DECL1
3 CP
4, 7, 11, 15, 20, 21, 23,
25, 28, 30, 31, 35
24
5
GND
NC
RSET
6 REFIN
8 MUXOUT
9 DECL2
12 DATA
Description
Power Supply Pins. The power supply voltage range is 4.75 V to 5.25 V. Drive all of
these pins from the same power supply voltage. Decouple each pin with 100 pF and
0.1 μF capacitors located close to the pin.
Decoupling Node for Internal 3.3 V LDO. Decouple this pin with 100 pF and 0.1 μF
capacitors located close to the pin.
Charge Pump Output Pin. Connect VTUNE to this pin through the loop filter. If
an external VCO is being used, connect the output of the loop filter to the VCO’s
voltage control pin. The PLL control loop should then be closed by routing the VCO’s
frequency output back into the ADRF6703 through the LON and LOP pins.
Ground. Connect these pins to a low impedance ground plane.
Do not connect to this pin.
Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA,
750 μA, or 1000 μA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (CP
reference source).
In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge
pump currents (INOMINAL) can be externally tweaked according to the following
equation:
R SET
=
⎜⎜⎝⎛
217.4 × I CP
I NOMINAL
⎟⎟⎠⎞
37.8Ω
where ICP is the base charge pump current in microamps. For further details on the
charge pump current, see the Register 4—PLL Charge Pump, PFD, and Reference Path
Control section.
Reference Input. The nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz.
This pin has high input impedance and should be ac-coupled. If REFIN is being driven
by laboratory test equipment, the pin should be externally terminated with a 50 Ω
resistor (place the ac-coupling capacitor between the pin and the resistor). When
driven from an 50 Ω RF signal generator, the recommended input level is 4 dBm.
Multiplexer Output. This output allows a digital lock detect signal, a voltage
proportional to absolute temperature (VPTAT), or a buffered, frequency-scaled
reference signal to be accessed externally. The output is selected by programming
DB21 to DB23 in Register 4.
Decoupling Node for 2.5 V LDO. Connect 100 pF, 0.1 μF, and 10 μF capacitors between this
pin and ground.
Serial Data Input. The serial data input is loaded MSB first with the three LSBs being
the control bits.
Rev. 0 | Page 8 of 36







ADRF6703 equivalent, schematic
ADRF6703
THEORY OF OPERATION
The ADRF6703 integrates a high performance IQ modulator
with a state of the art fractional-N PLL. The ADRF6703 also
integrates a low noise VCO. The programmable SPI port allows
the user to control the fractional-N PLL functions and the
modulator optimization functions. This includes the capability
to operate with an externally applied LO or VCO.
The quadrature modulator core within the ADRF6703 is a part
of the next generation of industry-leading modulators from
Analog Devices, Inc. The baseband inputs are converted to
currents and then mixed to RF using high performance NPN
transistors. The mixer output currents are transformed to a
single-ended RF output using an integrated RF transformer
balun. The high performance active mixer core, coupled with
the low-loss RF transformer balun results in an exceptional
OIP3 and OP1dB, with a very low output noise floor for excel-
lent dynamic range. The use of a passive transformer balun
rather than an active output stage leads to an improvement
in OIP3 with no sacrifice in noise floor. At 2140 MHz the
ADRF6703 typically provides an output P1dB of 14.2 dBm,
OIP3 of 33.2 dBm, and an output noise floor of −159.6 dBm/Hz.
Typical image rejection under these conditions is −52.3 dBc
with no additional I and Q gain compensation.
PLL + VCO
The fractional divide function of the PLL allows the frequency
multiplication value from REFIN to the LOP/LON outputs to
be a fractional value rather than restricted to an integer as in
traditional PLLs. In operation, this multiplication value is INT
+ (FRAC/MOD) where INT is the integer value, FRAC is the
fractional value, and MOD is the modulus value, all of which
are programmable via the SPI port. In previous fractional-N
PLL designs, the fractional multiplication was achieved by
periodically changing the fractional value in a deterministic
way. The downside of this was often spurious components close
to the fundamental signal. In the ADRF6703, a sigma delta
modulator is used to distribute the fractional value randomly,
thus significantly reducing the spurious content due to the
fractional function.
BASIC CONNECTIONS FOR OPERATION
Figure 35 shows the basic connections for operating the
ADRF6703 as they are implemented on the device’s evaluation
board. The seven power supply pins should be individually
decoupled using 100 pF and 0.1 μF capacitors located as close
as possible to the pins. A single 10 μF capacitor is also recom-
mended. The three internal decoupling nodes (labeled DECL3,
DECL2, and DECL1) should be individually decoupled with
capacitors as shown in Figure 35.
The four I and Q inputs should be driven with a bias level of
500 mV. These inputs are generally dc-coupled to the outputs of
a dual DAC (see the DAC-to-IQ Modulator Interfacing and IQ
Filtering sections for more information).
A 1 V p-p (0.353 V rms) differential sine wave on the I and Q
inputs results in a single sideband output power of 4.95 dBm (at
2140 MHz) at the RFOUT pin (this pin should be ac-coupled as
shown in Figure 35). This corresponds to an IQ modulator
voltage gain of 0.95 dB.
The reference frequency for the PLL (typically 1 V p-p between
12 MHz and 160 MHz) should be applied to the REFIN pin,
which should be ac-coupled. If the REFIN pin is being driven
from a 50 Ω source (for example, a lab signal generator), the
pin should be terminated with 50 Ω as shown in Figure 35 (an
RF drive level of +4 dBm should be applied). Multiples or
fractions of the REFIN signal can be brought back off-chip at
the multiplexer output pin (MUXOUT). A lock-detect signal
and an analog voltage proportional to the ambient temperature
can also be brought out on this pin by setting the appropriate
bits on (DB21-DB23) in Register 4 (see the Register Description
section).
EXTERNAL LO
The internally generated local oscillator (LO) signal can be
brought off-chip as either a 1× LO or a 2× LO (via pins LOP
and LON) by asserting the LOSEL pin and making the appro-
priate internal register settings. The LO output must be disabled
whenever the RF output of the IQ modulator is disabled.
The LOP and LON pins can also be used to apply an external
LO. This can be used to bypass the internal PLL/VCO or if
operation using an external VCO is desired. To turn off the
PLL Register 6, Bits[20:17] must be zero.
Rev. 0 | Page 16 of 36










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