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PDF ( 数据手册 , 数据表 ) ADM1168

零件编号 ADM1168
描述 Super Sequencer and Monitor
制造商 Analog Devices
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ADM1168 数据手册, 描述, 功能
Data Sheet
Super Sequencer and Monitor with
Nonvolatile Fault Recording
ADM1168
FEATURES
Complete supervisory and sequencing solution for up to
8 supplies
16 event deep black box nonvolatile fault recording
8 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
4 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP3 (VPx)
4 dual-function inputs, VX1 to VX4 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
8 programmable driver outputs, PDO1 to PDO8 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
NFET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 32-lead, 7 mm × 7 mm LQFP
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND SDA SCL A1 A0
ADM1168
VREF
SMBus
INTERFACE
FAULT RECORDING EEPROM
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
AGND
VDDCAP
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF NFET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDOGND
VCCP GND
Figure 1.
GENERAL DESCRIPTION
The ADM1168 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems.
The device also provides up to eight programmable inputs
for monitoring undervoltage faults, overvoltage faults, or
out-of-window faults on up to eight supplies. In addition, eight
programmable outputs can be used as logic enables. Six of these
programmable outputs can also provide up to a 12 V output for
driving the gate of an NFET that can be placed in the path of a
supply.
The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs based
on the condition of the inputs.
A block of nonvolatile EEPROM is available that can be used to
store user-defined information and may also be used to hold a
number of fault records that are written by the sequencing engine
defined by the user when a particular fault or sequence occurs.
The ADM1168 is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can be
programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
For more information about the ADM1168 register map, refer
to the AN-721 Application Note.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







ADM1168 pdf, 数据表
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADM1168
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
32
1
8
9
PIN 1
INDICATOR
ADM1168
TOP VIEW
(Not to Scale)
25
24 PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
17 PDO8
16
NC = NO CONNECT.
DO NOT CONNECT TO THIS PIN.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 4
VX1 to VX4
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.
5 to 7
VP1 to VP3
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation
on a potential divider connected to these pins, the output of which connects to a supply fault detector.
These pins allow thresholds from 2.5 V to 6 V, from 1.25 V to 3 V, and from 0.573 V to 1.375 V.
8 VH High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation
on a potential divider connected to this pin, the output of which connects to a supply fault detector.
This pin allows thresholds from 6 V to 14.4 V and from 2.5 V to 6 V.
9
AGND1
Ground Return for Input Attenuators.
10
REFGND1
Ground Return for On-Chip Reference Circuits.
11, 13 to 16 NC
No Connect. Do not connect to this pin.
12
REFOUT
Reference Output, 2.048 V. Note that a capacitor must always be connected between this pin and REFGND.
A 10 μF capacitor is recommended for this purpose.
17 to 24
PDO8 to PDO1 Programmable Output Drivers.
25
PDOGND1
Ground Return for Output Drivers.
26
VCCP
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin and
GND. A 10 μF capacitor is recommended for this purpose.
27 A0
Logic Input. This pin sets the seventh bit of the SMBus interface address.
28 A1
Logic Input. This pin sets the sixth bit of the SMBus interface address.
29 SCL
SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
30 SDA SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.
31
VDDCAP
Device Supply Voltage. Linearly regulated from the highest of the VPx and VH pins to a typical of 4.75 V.
A capacitor must be connected between this pin and GND. A 10 μF capacitor is recommended for
this purpose.
32
GND1
Supply Ground.
1 In a typical application, all ground pins are connected together.
Rev. B | Page 7 of 27







ADM1168 equivalent, schematic
Data Sheet
ADM1168
SEQUENCING ENGINE
OVERVIEW
The ADM1168 SE provides the user with powerful and flexible
control of sequencing. The SE implements a state machine control
of the PDO outputs with state changes conditional on input
events. SE programs can enable complex control of boards such
as power-up and power-down sequence control, fault event
handling, and interrupt generation on warnings. A watchdog
function that verifies the continued operation of a processor
clock can be integrated into the SE program. The SE can also be
controlled via the SMBus, giving software or firmware control
of the board sequencing.
The SE state machine comprises 63 state cells. Each state has the
following attributes:
It monitors signals indicating the status of the eight input
pins, VP1 to VP3, VH, and VX1 to VX4.
It can be entered from any other state.
Three exit routes move the state machine onto a next state:
sequence detection, fault monitoring, and timeout.
Delay timers for the sequence and timeout blocks can be
programmed independently and changed with each state
change. The range of timeouts is from 0 ms to 400 ms.
The output condition of the eight PDO pins is defined and
fixed within a state.
It can transition from one state to the next in less than
20 μs, which is the time needed to download a state
definition from EEPROM to the SE.
It can trigger a write of the black box fault and status
registers into the black box section of EEPROM.
MONITOR
FAULT
STATE
TIMEOUT
SEQUENCE
Figure 19. State Cell
The ADM1168 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the
outputs of the SFDs.
WARNINGS
The SE also monitors warnings. These warnings can be generated
when the ADC readings violate their limit register value or
when the secondary voltage monitors on VPx and VH are
triggered. The warnings are OR’ed together and are available
as a single warning input to each of the three blocks that enable
exiting a state.
SMBus JUMP (UNCONDITIONAL JUMP)
The SE can be forced to advance to the next state unconditionally.
This enables the user to force the SE to advance. Examples of
the use of this feature include moving to a margining state or
debugging a sequence. The SMBus jump or go-to command
can be seen as another input to sequence and timeout blocks to
provide an exit from each state.
Table 7. Sample Sequence State Entries
State Sequence
IDLE1 If VX1 is low, go to State IDLE2.
IDLE2 If VP1 is okay, go to State EN3V3.
EN3V3 If VP2 is okay, go to State EN2V5.
DIS3V3 If VX1 is high, go to State IDLE1.
EN2V5 If VP3 is okay, go to State PWRGD.
DIS2V5
FSEL1
FSEL2
PWRGD
If VX1 is high, go to State IDLE1.
If VP3 is not okay, go to State DIS2V5.
If VP2 is not okay, go to State DIS3V3.
If VX1 is high, go to State DIS2V5.
Timeout
If VP2 is not okay after 10 ms,
go to State DIS3V3.
If VP3 is not okay after 20 ms,
go to State DIS2V5.
Monitor
If VP1 is not okay, go to State IDLE1.
If VP1 or VP2 is not okay, go to State FSEL2.
If VP1 or VP2 is not okay, go to State FSEL2.
If VP1 is not okay, go to State IDLE1.
If VP1, VP2, or VP3 is not okay, go to State FSEL1.
Rev. B | Page 15 of 27










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