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零件编号 | AD6641 | ||
描述 | 250 MHz Bandwidth DPD Observation Receiver | ||
制造商 | Analog Devices | ||
LOGO | |||
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250 MHz Bandwidth
DPD Observation Receiver
AD6641
FEATURES
GENERAL DESCRIPTION
SNR = 65.8 dBFS at fIN up to 250 MHz at 500 MSPS
ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
SFDR = 80 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
Excellent linearity
DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical
Integrated 16k × 12 FIFO
FIFO readback options
12-bit parallel CMOS at 62.5 MHz
6-bit DDR LVDS interface
SPORT at 62.5 MHz
SPI at 25 MHz
High speed synchronization capability
1 GHz full power analog bandwidth
Integrated input buffer
On-chip reference, no external decoupling required
Low power dissipation
695 mW at 500 MSPS
Programmable input voltage range
1.18 V to 1.6 V, 1.5 V nominal
1.9 V analog and digital supply operation
1.9 V or 3.3 V SPI and SPORT operation
Clock duty cycle stabilizer
Integrated data clock output with programmable clock and
data alignment
The AD6641 is a 250 MHz bandwidth digital predistortion
(DPD) observation receiver that integrates a 12-bit 500 MSPS
ADC, a 16k × 12 FIFO, and a multimode back end that allows
users to retrieve the data through a serial port (SPORT), the SPI
interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS
port after being stored in the integrated FIFO memory. It is opti-
mized for outstanding dynamic performance and low power
consumption and is suitable for use in telecommunications
applications such as a digital predistortion observation path
where wider bandwidths are desired. All necessary functions,
including the sample-and-hold and voltage reference, are
included on the chip to provide a complete signal conversion
solution.
The on-chip FIFO allows small snapshots of time to be captured
via the ADC and read back at a lower rate. This reduces the
constraints of signal processing by transferring the captured
data at an arbitrary time and at a much lower sample rate. The
FIFO can be operated in several user-programmable modes. In
the single capture mode, the ADC data is captured when sig-
naled via the SPI port or the use of the external FILL± pins. In
the continuous capture mode, the data is loaded continuously
into the FIFO and the FILL± pins are used to stop this operation.
APPLICATIONS
Wireless and wired broadband communications
Communications test equipment
Power amplifier linearization
FUNCTIONAL BLOCK DIAGRAM
FILL+ FILL– DUMP
CLK+
CLK–
VIN+
VIN–
CLOCK AND CONTROL
ADC
FIFO
16k × 12
PARALLEL
AND
SPORT
OUTPUTS
SPI CONTROL
REFERENCE AND DATA
VREF SCLK, SDIO, AND CSB
Figure 1.
PCLK+
PCLK–
PD[5:0]± IN DDR LVDS MODE
OR PD[11:0] IN CMOS MODE
SP_SCLK
SP_SDFS
SP_SDO
FULL
EMPTY
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD6641
SPI TIMING REQUIREMENTS
Table 5.
Parameter
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge
Timing Diagrams
N–1
VIN±
tA
N
CLK+
CLK–
tCH tCL
N+1
N+2
Figure 2. Input Interface Timing
N+3
N+4
CLK+
CLK–
PCLK+
PCLK–
PD[11:0]
OUTPUT DATA BUS
tCPD
tSKEW
tPCLK_CH
tPCLK
Figure 3. Parallel CMOS Mode Output Interface Timing
SP_SCLK
SP_SDFS
tDSDFS
Figure 4. SP_SDFS Propagation Delay
Limit
2
2
40
2
2
10
10
10
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
N+5
Rev. 0 | Page 8 of 28
AD6641
95
90
SFDR (dBc)
85
80
75
70
SNR (dBFS)
65
60
55
SFDR @ 30.3MHz, 1.8V
SFDR @ 30.3MHz, 1.9V
SFDR @ 100.3MHz, 1.8V
SFDR @ 100.3MHz, 1.9V
SNRFS @ 30.3MHz, 1.8V
SNRFS @ 30.3MHz, 1.9V
SNRFS @ 100.3MHz, 1.8V
SNRFS @ 100.3MHz, 1.9V
50
250 300 350 400 450 500
SAMPLE RATE (MSPS)
Figure 16. SNR/SFDR vs. Sample Rate and Supply
550
100
90
SFDR (dBFS)
80
70 SNR (dBFS)
60
50
40 SFDR (dBc)
SNRFS, 1.9V
30 SNR, 1.9V
SFDR, 1.9V
20
SNR (dB)
10
SFDRFS, 1.9V
SNRFS, 1.8V
SNR, 1.8V
SFDR, 1.8V
SFDRFS, 1.8V
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
0
AMPLITUDE (dB)
Figure 17. SNR/SFDR vs. Input Amplitude; 500 MSPS,140.3 MHz
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
1023
2047
OUTPUT CODE
3071
Figure 18. INL; 500 MSPS
4095
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–1
2.5
2.0
1023
2047
OUTPUT CODE
3071
Figure 19. DNL; 500 MSPS
4095
1.24 LSB rms
1.5
1.0
0.5
0
N–3 N–2 N–1
N N + 1 N + 2 N + 3 MORE
BINS
Figure 20. Grounded Input Histogram; 500 MSPS
491.52MSPS
0 fIN1: 121.3MHz @ –7dBFS
fIN2: 124.7MHz @ –7dBFS
–15 SFDR: 85dBc
–30
–45
–60
–75
–90
–105
–120
25 50 75 100 125 150 175 200 225
FREQUENCY (MHz)
Figure 21. 16k Point Single-Tone FFT; 491.52 MSPS,
fIN1 = 121.3 MHz, fIN2 = 124.7 MHz
Rev. 0 | Page 16 of 28
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页数 | 28 页 | ||
下载 | [ AD6641.PDF 数据手册 ] |
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