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PDF ( 数据手册 , 数据表 ) ML12202

零件编号 ML12202
描述 MECL PLL Components Serial Input PLL Frequency Synthesizer
制造商 LANSDALE Semiconductor
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ML12202 数据手册, 描述, 功能
ML12202
MECL PLL Components Serial
Input PLL Frequency Synthesizer
Legacy Device: Motorola MC12202
The ML12202 is a 1.1 GHz Bipolar monolithic serial input
phase locked loop (PLL) synthesizer with pulse–swallow func-
tion. It is designed to provide the high frequency local oscillator
signal of an RF transceiver in handheld communication applica-
tions.
The technology is utilized allows for low power operation at a
minimum supply voltage of 2.7 V. The device is designed for
operation over 2.7 to 5.5 V supply range for input frequencies up
to 1.1 GHz with a typical current drain of 6.5 mA. The low
power consumption makes the ML12202 ideal for handheld bat-
tery operated applications such as cellular or cordless tele-
phones, wireless LAN or personal communication services. A
dual modulus prescaler is integrated to provide either a 64/65 or
128/129 divide ratio.
• Low Power Supply Current of 5.8 mA Typical for ICC and
0.7 mA Typical for IP
• Supply Voltage of 2.7 to 5.5 V
• Dual Modulus Prescaler With Selectable Divide Ratios of
64/65 or128/129
• On–Chip Reference Oscillator/Buffer
• Programmable Reference Divider Consisting of a Binary
14–Bit Programmable Reference Counter
• Programmable Divider Consisting of a Binary 7–Bit
Swallow Counter and an 11–Bit Programmable Counter
• Phase/Frequency Detector With Phase Conversion Function
• Balanced Charge Pump Outputs
• Dual Internal Charge Pumps for Bypassing the First Stage of
the Loop Filter to Decrease Lock Time
• Outputs for External Charge Pump
• Operating Temperature Range of TA = –40 to 85°C
NOTE: Also available is the ML12210, a 2.5 GHz version of
this function.
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
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ML12202 pdf, 数据表
ML12202
LANSDALE Semiconductor, Inc.
LOCK DETECT
The Lock Detect (LD) output pin provides a LOW pulse when fr and fp are not equal in phase or frequency. The output is nor-
mally HIGH. LD is designed to be the logical NORing of the phase frequency detector’s outputs UP and DOWN. See Figure 6.
In typical applications the output signal drives external circuitry which provides a steady LOW signal when the loop is locked.
See Figure 9.
OSCILLATOR INPUT
For best operation, an external reference oscillator is recommended. The signal should be AC–coupled to the OSCin pin through
a coupling capacitor. In this case, no connection to OSCout is required. The magnitude of the AC–coupled signal must be
between 500 and 2200 mV peak–to–peak. To optimize the phase noise of the PLL when used in this mode, the input signal
amplitude should be closer to the upper specification limit. This maximizes the slew rate of the signal as it switches against the
internal voltage reference.
The device incorporates an on–chip reference oscillator/buffer so that an external parallel–resonant fundamental crystal can be
connected between OSCin and OSCout. External capacitor C1 and C2 as shown in Figure 10 are required to set the proper crys-
tal load capacitance and oscillator frequency. The values of the capacitors are dependent on the crystal chosen (up to a maximum
of 30 pF each including parasitic and stray capacitance). However, using the on–chip reference oscillator, greatly increases the
synthesized phase noise.
DUAL INTERNAL CHARGE PUMPS (“ANALOG SWITCH”)
Due to the pure Bipolar nature of the ML12202 design, the “analog switch” function is implemented with dual internal charge
pumps. The loop filter time constant can be decreased by bypassing the first stage of the loop filter with the charge pump output
BISW as shown in Figure 7 below. This enables the VCO to lock in a shorter amount of time.
When LE is HIGH or OPEN (“analog switch is ON”), the output of the second internal charge pump is connected to the BISW
pin, and the Do output is ON. The charge pump 2 output on BISW is essentially equal to the charge pump 1 output on Do. When
LE is LOW, BISW is in a high impedance state and Do output is active.
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