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PDF ( 数据手册 , 数据表 ) YSS950

零件编号 YSS950
描述 DAP1 Digital Audio Processor
制造商 YAMAHA
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YSS950 数据手册, 描述, 功能
YSS950
DAP1
Digital Audio Processor
Outline
The YSS950 (DAP1) is a DSP (Digital Signal Processor) for sound field processing, which features a
high-speed/ high-precision 32-bit floating point DSP.
Features
{ 32-bit floating point DSP achieves high-speed/high-precision operations
Operation frequency: Approximately 166 MHz
Data bus width: 32 bits (24-bit mantissa, 8-bit exponent)
Multiplier/adder: 32 bits × 32 bits + 55 bits 55 bits (47-bit mantissa, 8-bit exponent)
{ 48 KB (12 Kword) preset command code firmware area
{ 24 KB (6 Kword) download command code firmware area (maximum)
{ 104 KB (26 Kword) data RAM area (maximum)
{ High-speed command code/coefficient data firmware download (burst transfer)
{ Download coefficients data firmware without any interruption of sound (runtime transfer)
{ Firmware’s placement order can be changed
{ Firmware’s number of execution channels can be changed (up to 16 channels)
{ Multiple firmware calls are enabled
{ Audio I/O
32 bits × 16 channels, TDM
Fixed point decimal format and floating point decimal format (IEEE Standard 754, two’s complement)
Sampling frequency range is 32 to 192 kHz
Audio clock division/switch
Input/output muting
Input/output channel switching
{ External memory not required
{ General I/O ports (4)
{ On-chip PLL
{ Power supply voltage: 1.2 V (core), 3.3 V (pin)
{ Low power consumption: Approximately 130mW (typical value)
{ Si-gate CMOS process
{ Lead-free 64-pin SQFP package (YSS950-SZ)
Applications
{ Home theater systems
{ Car audio
www.DataSheet4U.com
YSS950 CATALOG
CATALOG No.: LSI-4SS950A22
2006.10







YSS950 pdf, 数据表
YSS950
Type
Power supply
Pin Pin Name I/O
Function
No. Note 1)
26 VDD33
Digital power supply for pin block (Typ. 3.3 V)
39
55
9 VDD12
24
Digital power supply for Core block (Typ. 1.2 V)
25
40
41
56
57
62 PAVDD
64
Power supply for PLL analog block (Typ. 1.2 V)
Insert a 0.1 µF capacitor between the PAVDD and PAVSS pins.
3 PDVDD
Power supply for PLL digital block (Typ. 1.2 V)
Insert a 0.1 µF capacitor between the PDVDD and PDVSS pins.
4 VSS
16
Digital ground
17
32
33
48
49
61
1 PAVSS
63
PLL analog ground
Insert a 0.1 µF capacitor between the PAVDD and PAVSS pins.
2 PDVSS
PLL digital ground
Insert a 0.1 µF capacitor between the PDVDD and PDVSS pins.
Note 1)
I/O symbols
* Built in pull-up circuit cannot be used for Hi-level output of the LSI, because of this ability is only keep Hi-level for input pin
when it is open.
Note 2) Example of circuit connected to crystal oscillator
XI XO
12.288 MHz
* The above resistor and capacitor values vary depending on a crystal oscillator. Be sure to meet the
specifications for the crystal oscillator to be used.
8







YSS950 equivalent, schematic
YSS950
(b) Interface format
1) Input format
The normal mode timing is illustrated below. 32-bit data can be input via the two channels from SDI0, SDI1,
SDI2, SDI3, SDI4, SDI5, SDI6, and SDI7. (n) indicates the current frame input sample and (n 1) indicates
the previous frame input sample.
1 frame (1/fs = 64 SDIBCKs)
SDIWCK SDIWCKP=0
SDIWCKP=1
SDIBCK SDIBCKP=0
32 SDIBCKs
32 SDIBCKs
SDI*
SDIBCKP=1
SDITFMT=0b00
SDIBIT=0bxx
SDITFMT=0b10
SDIBIT=0bxx
SDITFMT=0b01
SDIBIT=0b00
SDITFMT=0b01
SDIBIT=0b01
SDITFMT=0b01
SDIBIT=0b10
SDITFMT=0b01
SDIBIT=0b11
SDI*L(n)
SDI*R(n)
M
S
B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
LM
SS
BB
1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 14 12
L
S
B
10
SDI*L(n)
SDI*R(n)
M
S
B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
L
S
B
2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
L
S
B
210
SDI*R(n-1)
SDI*L(n)
SDI*R(n)
LM
SS
BB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28
LM
SS
BB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28
17 16
SDI*R(n-1)
SDI*L(n)
SDI*R(n)
LM
SS
BB
13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26
LM
SS
BB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26
15 14
SDI*R(n-1)
SDI*L(n)
SDI*R(n)
LM
SS
BB
11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
LM
SS
BB
13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
13 12
SDI*R(n-1)
SDI*L(n)
SDI*R(n)
LM
SS
BB
7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20
LM
SS
BB
9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20
98
16










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