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PDF ( 数据手册 , 数据表 ) YSS940

零件编号 YSS940
描述 (YSS940 - YSS944) ADAMB Advanced Digital Audio Multi channel decode processor
制造商 YAMAHA
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YSS940 数据手册, 描述, 功能
YSS944/943/940
ADAMB
Advanced Digital Audio Multi channel decode processor
„ Outline
The YSS944 (ADAMB-f)/YSS943 (ADAMB-b)/YSS940 (ADAMB-nd) is an audio decoding digital signal
processor that integrates onto a single chip the various digital signal processing functions required for AV
amplifiers, etc. It includes an advanced 32-bit floating-point DSP and is able to decode a variety of audio
formats.
[Note]
The contents described in this manual are implemented by downloading boot firmware.
For detailed information about the boot firmware, please contact YAMAHA.
The YSS943 cannot execute DTS-ES and DTS Neo:6 decoding.
The YSS940 cannot execute any decoding related to DTS (DTS, DTS-ES, DTS 96/24, and DTS Neo:6).
„ Features
Supports various types of decoding up to 7.1 channels (5.1/6.1/7.1 channels selectable).
5.1-channel decoding of Dolby Digital (AC-3), DTS, AAC.
6.1-channel decoding of Dolby Digital EX, DTS-ES.
DTS 96/24 decoding and audio interface clock division/switching functions.
Dolby Pro Logic IIx and DTS Neo:6 decoding
Tone control and bass management functions
Function modification/expansion by downloading firmware to on-chip memory
Lip-sync function that enables synchronization of voice and video with variable voice delay
Supports sampling frequencies up to 192 kHz during PCM playback.
1/2 down sampling function when two PCM channels are played back
Dolby Digital/DTS/AAC decode information output function (can be read by microprocessor)
High-speed/high-accuracy operation by 32-bit floating-point DSP
Operating frequency: 180 MHz (178.176 MHz)
Data bus width: 32 bits (24-bit mantissa and 8-bit exponent)
Multiplier/adder: 32 bits × 32 bits + 55 bits 55 bits (47-bit mantissa and 8-bit exponent)
No external memory needed (external memory is used when delay is increased.)
Eight general I/O ports
On-chip PLL for generation of high-speed internal operating clock
Supply voltage: 1.2 V (core block) and 3.3 V (pin block)
Low power consumption: about 210 mW (standard value during Dolby Digital decoding)
Si-gate CMOS process
Lead-free plating LQFP144 package (YSS944-VZ, YSS943-VZ, and YSS940-VZ)
[Note]
“Dolby,” ”Dolby Pro Logic IIx,” and “AC-3” are trademarks of Dolby Laboratories.
“DTS,” “DTS-ES,” “DTS 96/24,” and “DTS Neo:6” are trademarks of Digital Theater Systems, Inc.
„ Applications
AV amplifiers for home theaters
Car audio systems
www.DataSheet4U.com
YSS944/943/940 CATALOG
CATALOG No.: LSI-4SS944A31
2005.6







YSS940 pdf, 数据表
YSS944/943/940
Type
General-purpose
I/O ports
General-purpose
I/O ports
Test
Pin Pin Name I/O
Function
No. Note 1)
135 nMUTE
O This is the output pin during auto mute periods.
133 ZEROFLG O This is the consecutive zero data input detection pin.
13 STATUS7 O These are status output pins 7 to 0.
12 STATUS6
They are used to confirm firmware operations.
11 STATUS5
Normally, they should be left unconnected.
10 STATUS4
116 STATUS3
115 STATUS2
114 STATUS1
113 STATUS0
57 IOPORT7 I(+)/O These are general I/O port pins 7 to 0.
56 IOPORT6
Their I/O status can be set via register settings.
55 IOPORT5 I(+)/O These are general I/O port pins 7 to 0.
54 IOPORT4
Their I/O status can be set via register settings.
53 IOPORT3
52 IOPORT2
47 IOPORT1
46 IOPORT0
16 TEST
Is Test pins
17 Connect these pins to a ground.
24
25
132
Note 1) I/O symbols
I: Input
Is: Schmitt trigger input
O: Output
Ot: Tri-state output
I/O: I/O
I(+)/O: Pull-up during input, no pull-up during output
Note 2) Example of circuit connected to crystal oscillator
XI XO
12.288 MHz
* The above resistor and capacitor vary depending on the crystal oscillator. Be sure to comply with the specifications of the
crystal oscillator used.
8







YSS940 equivalent, schematic
YSS944/943/940
(b) Microprocessor interface connection example 2 (multiple LSIs)
nMICS
Chip 2
When multiple LSIs are connected such as on
the left, or when the device has a similar
interface, access is performed using the register
Chip 3 byte ChipAdr (CAE, CA[3:0]).
IOPORT3 to IOPORT0 = 2
IOPORT3 to IOPORT0 = 3
n MICS
MI SI
CAE
(Chip 2, 3)
Internal signal
nMICS (Chip 2)
Internal signal
nMICS (Chip 3)
<1> <2>
<3>
<4> <5>
Write ChipAdr
CAE = 1
CA[3:0] = 0011
0
Write ChipAdr
CAE = 1
CA[3:0] = 0010
Read ChipAdr
CAE = 1
CA[3:0] = 0011
1
On-chip memory access
0
<1> A write operation to ChipAdr as the register access immediately after the falling edge of nMICS is
valid to for all LSIs (chips 2 and 3 in this example) that share the nMICS pin. In this case, CAE = 1
and CA[3:0] = 3, so only the access only for chip 3 is valid.
<2> A write operation to ChipAdr not immediately after the falling edge of nMICS is also invalid for chip
3.
(Chip 2 is not affected by the register access itself.)
<3> The ChipAdr register can be read at any time. In this case, the write results from <1> are read from
chip 3.
(Chip 2 is not affected by the register access itself.)
<4> During on-chip memory access, register access for chip 3 is invalid.
(Chip 2 is not affected by on-chip memory access.)
<5> CAE of all LSIs becomes zero at the rising edge of nMICS.
[Note]
The timing by which the chip selection is confirmed in <1> is determined by the value of IOPORT3 to
IOPORT0 either at:
the register access immediately after falling edge of nMICS, or
a write operation to ChipAdr.
Once the chip selection is confirmed, the current value is retained until the next rising edge of nMICS.
Accordingly, even if the selected chip’s own IOPORT3 to IOPORT0 values change, the chip does not
become deselected immediately.
When nMICS is shared by multiple chips:
CAE = 0 at the register access immediately after the falling edge of nMICS or CAE = 1 is not written.
CAE = 1 at the register access immediately after the falling edge of nMICS, but the values of IOPORT3
to IOPORT0 are the same for multiple LSIs.
In the above cases, the multiple LSIs that share nMICS become the selected devices. In such cases,
multiple LSIs can be written to at once, but note with caution that a conflict can occur with the MISO output
when they are read.
16










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